Freescale Semiconductor MCF5329 Reference Manual page 171

Because the operation of the crossbar switch and the system control module (SCM) are fundamental to the
operation of the device, the clocks for these modules cannot be disabled.
The individual bits of the PPMR can be modified using a read-modify-write to this register directly or
indirectly through writes to the PPMSR and PPMCR registers to set/clear individual bits.
Address: 0xFC04_0038 (PPMHR1)
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Figure 8-4. Peripheral Power Management High Register (PPMHR1)
Slot Number
Address: 0xFC04_0030 (PPMHR0)
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R
CD47 CD46 CD45 CD44 CD43 CD42 CD41 CD40
W
Reset 0 0 0
Figure 8-5. Peripheral Power Management High Register (PPMHR0)
Slot Number
Freescale Semiconductor
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
Table 8-5. PPMHR1[CDn] Assignments
CDn
32 CD32
33 CD33
34 CD34
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
0 0 0 0
Table 8-6. PPMHR0[CDn] Assignments
CDn
32 CD32
33 CD33
34 CD34
35 CD35
MCF5329 Reference Manual, Rev 3
24 23 22 21
0 0 0 0
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
Peripheral
MDHA
SKHA
Random Number Generator
24 23 22 21
0 0 0 0
0 0 0 0
8 7 6 5
0
CD38 CD37 CD36 CD35 CD34 CD33 CD32
0 0 0 0
Peripheral
PIT 0
PIT 1
PIT 2
PIT 3
Power Management
Access: Supervisor read/write
20 19 18 17
0 0 0 0
0 0 0 0
4 3 2 1
0 0
CD34 CD33 CD32
0 0 0 0
Access: Supervisor read/write
20 19 18 17
0 0 0 0
CD48
0 0 0 0
4 3 2 1
0 0 0 0
16
0
0
0
0
16
0
0
0
8-5