Read Clock Recovery (Rcr) Block - Freescale Semiconductor MCF5329 Reference Manual

SDRAM Controller (SDRAMC)
18.5.1.8 Self-Refresh (SREF) and Power Down (PDWN) Commands
The memory controller issues a PDWN or a SREF command if the SDCR[CKE] bit is cleared. If the
SDCR[REF_EN] bit is set when CKE is negated, the controller issues a SREF command; if the REF_EN
bit is cleared, the controller issues a PDWN command. The REF_EN bit may be changed in the same
register write that changes the CKE bit; the controller acts upon the new value of the REF_EN bit.
Like an auto-refresh command, the controller automatically issues a
command.
The memory reactivates from power-down or self-refresh mode by setting the CKE bit.
If a normal refresh interval elapses while the memory is in self-refresh mode, a PALL and REF performs
when the memory reactivates. If the memory is put into and brought out of self-refresh all within a
single-refresh interval, the next automatic refresh occurs on schedule.
In self-refresh mode, memory does not require an external clock. The SD_CLK can be stopped for
maximum power savings. If the memory controller clock is stopped, the refresh-interval timer must be
reset before the memory is reactivated (if periodic refresh is to be resumed). The refresh-interval timer
resets by clearing the REF_EN bit. This can be done at any time while the memory is in self-refresh mode,
before or after the memory controller clock is stopped/restarted, but not with the same control register
write that clears CKE; this would put the memory in power down mode. To restart periodic refresh when
the memory reactivates, the REF_EN bit must be reasserted; this can be done before the memory
reactivates or in the same control register write that sets CKE to exit self-refresh mode.
18.5.2

Read Clock Recovery (RCR) Block

The RCR block allows the external DDR memory devices to generate clock pulses (strobes) that define
the data valid window for each DDR data cycle. The RCR delay block compensates for each byte lane and
generates an internal read strobe targeted to the center of the data valid window provided by the external
DDR memories.
Figure 18-12 displays a simple timing diagram that illustrates the end result of the RCR delay.
Memory
Clock
t
CLK
SD_DQSn
rd_clk
(internal signal)
18-26
t
CLK
/2 t /2
CLK
t
CLK
t /4
CLK
t /4
CLK
MCF5329 Reference Manual, Rev 3
command before the self-refresh
PALL
Don't Care
t /2 t /2
CLK CLK
t /2 t /2
CLK CLK
Freescale Semiconductor