Freescale Semiconductor MCF5329 Reference Manual page 262

General Purpose I/O Module
13.3.6 FlexBus Mode Select Control Register (MSCR_FLEXBUS)
The MSCR_FLEXBUS register controls the output mode selects of the following FlexBus pins:
FB_A[23:0], D[31:0], BE/BWE[3:0], OE, R/W, FB_CS[5:0], TA and TS.
Address: 0xFC0A_4064 (MSCR_FLEXBUS)
7
R 0
W
Reset: 0
Figure 13-47. FlexBus Mode Select Control Register (MSCR_FLEXBUS)
Field
7–6 Reserved, should be cleared.
5–4 FB_D[31:16] mode select control. These bit fields control the strength of the FlexBus upper data pins.
MSCR_ 00 Half strength 1.8V low power/mobile DDR.
DUPPER 01 Open drain.
10 Full strength 1.8V low power/mobile DDR.
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.
3–2 FB_D[15:0] mode select control. These bit fields control the strength of the FlexBus lower data pins.
MSCR_ 00 Half strength 1.8V low power/mobile DDR.
DLOWER 01 Open drain.
10 Full strength 1.8V low power/mobile DDR.
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.
1–0 FB_A[23:0], BE/BWE[3:0], OE, R/W, FB_CS[5:0], TA, and TS mode select control. These bit fields control the
MSCR_ strength of the FlexBus address and control pins.
ADDRCTL 00 Half strength 1.8V low power/mobile DDR.
01 Open drain.
10 Full strength 1.8V low power/mobile DDR.
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.
13.3.7 SDRAM Mode Select Control Register (MSCR_SDRAM)
The MSCR_SDRAM register controls the output mode selects of the following dedicated SDRAM pins:
SD_A10, SD_CAS, SD_CKE, SD_CLK, SD_CLK, SD_CS0, SD_DQS[3:2], SD_RAS, SD_SDRDQS,
and SD_WE.
Address: 0xFC0A_4065 (MSCR_SDRAM)
7
R 0
W
Reset: 0
Figure 13-48. SDRAM Mode Select Control Register (MSCR_SDRAM)
13-34
6 5 4
0
MSCR_DUPPER
0 1 1
Table 13-21. MSCR_FLEXBUS Field Descriptions
Description
6 5 4
0
MSCR_SDCLKB
0 1 1
MCF5329 Reference Manual, Rev 3
Access: User read/write
3 2 1
MSCR_DLOWER MSCR_ADDRCTL
1 1 1
Access: User read/write
3 2 1
MSCR_SDCLK MSCR_SDRAM
1 1 1
Freescale Semiconductor
0
1
0
1