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Watchdog Timer Module
27.1.2
Block Diagram
Internal Bus
Clock
(f
)
sys/3
27.2
Memory Map/Register Definition
This subsection describes the memory map and registers for the watchdog timer. Refer to
an overview of the watchdog memory map.
Longword accesses to any of the watchdog timer registers result in a bus
error. Only byte and word accesses are allowed.
1
Address
0xFC09_8000 Watchdog Control Register (WCR)
0xFC09_8002 Watchdog Modulus Register (WMR)
0xFC09_8004 Watchdog Count Register (WCNTR)
0xFC09_8006 Watchdog Service Register (WSR)
1
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved
address spaces and reserved register bits have no effect.
27-2
Internal Bus
16-bit WCNTR
Divide by
16-bit Watchdog Counter
4096
EN
WAIT
DOZE
16-bit WMR
HALTED
Internal Bus
Figure 27-1. Watchdog Timer Block Diagram
NOTE
Table 27-2. Watchdog Timer Module Memory Map
Register
Supervisor Only Access
Supervisor/User Access
MCF5329 Reference Manual, Rev 3
16-bit WSR
Count = 0
Reset
Load Counter
Width
Access Reset Value Section/Page
(bits)
16
R/W
0x000F
16
R/W
0xFFFF
16
R
0xFFFF
16
R/W
0x0000
Freescale Semiconductor
Table 27-2
for
27.2.1/27-3
27.2.2/27-4
27.2.3/27-4
27.2.4/27-5
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