Freescale Semiconductor MCF5329 Reference Manual page 635

The following settings are done automatically by the processor when in I
• Normal mode is selected (SSI_CR[NET] = 0)
• Tx frame sync length set to one-bit-long-frame (SSI_TCR[TFSL] = 1)
• Rx frame sync length set to one-bit-long-frame (SSI_RCR[RFSL] = 1)
• Tx shifting w.r.t. bit 0 of TXSR (SSI_TCR[TXBIT0] = 1)
• Rx shifting w.r.t. bit 0 of RXSR (SSI_RCR[RXBIT0] = 1)
Set the SSI_CCR[WL, DC] bits to configure the data transmission.
The word length is variable in I
valid data. The actual word length is determined by the external codec. The external I
frame sync according to the I
so each frame sync transition is the start of a new frame (the WL bits determine the number of bits to be
transmitted/received). After one data word has been transferred, the SSI waits for the next frame sync
transition to start operation in the next time slot. Transmit and receive mask bits should not be used in I
slave mode.
24.4.1.5 AC97 Mode
In AC97 mode, SSI transmits a 16-bit tag slot at the start of a frame and the rest of the slots (in that frame)
are all 20-bits wide. The same sequence is followed while receiving data. Refer to the AC97 specification
for details regarding transmit and receive sequences and data formats.
Since the SSI has only one RxDATA pin, only one codec is supported.
Secondary codecs are not supported.
When AC97 mode is enabled, the hardware internally overrides the following settings. The programmed
register values are not changed by entering AC97 mode, but they no longer apply to the module's
operation. Writing to the programmed register fields updates their values. These updates can be seen by
reading back the register fields. However, these settings do not take effect until AC97 mode is turned off.
The register bits within the bracket are equivalent settings.
• Synchronous mode is entered (SSI_CR[SYN] = 1)
• Network mode is selected (SSI_CR[NET] = 1)
• Tx shift direction is msb transmitted first (SSI_TCR[TSHFD] = 0)
• Rx shift direction is msb received first (SSI_RCR[RSHFD] = 0)
• Tx data is clocked at rising edge of the clock (SSI_TCR[TSCKP] = 0)
• Rx data is latched at falling edge of the clock (SSI_RCR[RSCKP] = 0)
• Tx frame sync is active high (SSI_TCR[TFSI] = 0)
• Rx frame sync is active high (SSI_RCR[RFSI] = 0)
• Tx frame sync length is one-word-long-frame (SSI_TCR[TFSL] = 0)
• Rx frame sync length is one-word-long-frame (SSI_RCR[RFSL] = 0)
• Tx frame sync initiated one bit before data is transmitted (SSI_TCR[TEFS] = 1)
Freescale Semiconductor
2
S slave mode and the WL bits determine the number of bits that contain
2
S protocol (early, word wide, and active low). The SSI internally operates
NOTE
MCF5329 Reference Manual, Rev 3
Synchronous Serial Interface (SSI)
2
S slave mode:
2
S master sends a
2
S
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