Freescale Semiconductor MCF5329 Reference Manual page 632

Synchronous Serial Interface (SSI)
sections with internal or external clock and in normal mode. Gated clocks are not allowed in network
mode. Refer to Table 24-3
The clock operates when the TE bit and/or the RE bit are appropriately enabled. For an internally generated
clock, all internal bit clocks, word clocks, and frame clocks continue to operate. When a valid time slot
occurs (such as the first time slot in normal mode), the internal bit clock is enabled onto the clock port.
This allows data to be transferred out in periodic intervals in gated clock mode. With an external clock, the
SSI module waits for a clock signal to be received. After the clock begins, valid data is shifted in. Care
should be taken to clear all DC bits when the module is used in gated mode.
For gated clock operated in external clock mode, proper clock signalling must apply to SSI_BCLK for it
to function properly. If the SSI uses rising edge transition to clock data (TSCKP = 0) and falling edge
transition to latch data (RSCKP = 0), the clock must be in an active low state when idle. If the SSI uses
falling edge transition to clock data (TSCKP = 1) and rising edge transition to latch data (RSCKP = 1), the
clock must be in a active high state when idle. The following diagrams illustrate the different edge
clocking/latching.
SSI_BCLK
SSI_TXD
SSI_RXD
TSCKP=0, RSCKP=0
Figure 24-31. Internal Gated Mode Timing - Rising Edge Clocking/Falling Edge Latching
SSI_BCLK
SSI_TXD
SSI_RXD
TSCKP=1, RSCKP=1
Figure 24-32. Internal Gated Mode Timing - Falling Edge Clocking/Rising Edge Latching
SSI_BCLK
SSI_TXD
SSI_RXD
TSCKP=0, RSCKP=0
Figure 24-33. External Gated Mode Timing - Rising Edge Clocking/Falling Edge Latching
24-38
for SSI configuration for gated mode operation.
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor