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6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
For more information, see
14.4
Initialization/Application Information
The interrupt controller's reset state has all requests masked via the IMR. Before any interrupt requests are
enabled, the following steps must be taken:
1. Set the ICONFIG register to the desired system configuration.
2. Program the ICRn registers with the appropriate interrupt levels.
3. The reset value for the level mask registers (CLMASK and SLMASK) is 0xF (no levels masked).
Typically, these registers do not need to be modified before interrupts are enabled.
4. Load the appropriate interrupt vector tables and interrupt service routines into memory.
5. Enable the interrupt requests, by clearing the appropriate bits in the IMR and lowering the interrupt
mask level in the core's status register (SR[I]) to an appropriate level.
14.4.1
Interrupt Service Routines
This section focuses on the interaction of the interrupt masking functionality with the service routine.
Figure 14-14
presents a timing diagram showing various phases during the execution of an interrupt
service routine with the controller level masking functionality enabled. The time scale in this diagram is
not meant to be accurate.
A
Interrupt
Request
Core
Activity
SR[I]
0xF
CLMASK
SLMASK
Interrupts
Enabled
Note: Not to scale
Consider the events depicted in each segment (A – F) of the above diagram.
In A, an interrupt request is asserted, which is then signalled to the core.
As B begins, the interrupt request is recognized, and the core begins interrupt exception processing. During
the core's exception processing, the IACK cycle performs and the interrupt controller returns the
Freescale Semiconductor
Section 8.2.1, "Wake-up Control Register".
B
Interrupt Service Routine
iack
≤ n Disabled
Figure 14-14. Interrupt Service Routine and Masking
MCF5329 Reference Manual, Rev 3
C
D
n
n
0xF
Interrupt Controller Modules
E
F
swiack
n
0xF
14-19
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