Table 3-15. Two Operand Instruction Execution Times (continued)
Opcode
<EA>
CMP.L
<ea>,Rx
CMPI.L
#imm,Dx
DIVS.W
<ea>,Dx
DIVU.W
<ea>,Dx
DIVS.L
<ea>,Dx
DIVU.L
<ea>,Dx
EOR.L
Dy,<ea>
EORI.L
#imm,Dx
LEA
<ea>,Ax
LSL.L
<ea>,Dx
LSR.L
<ea>,Dx
MOVEQ.L
#imm,Dx
OR.L
<ea>,Rx
OR.L
Dy,<ea>
ORI.L
#imm,Dx
REMS.L
<ea>,Dx
REMU.L
<ea>,Dx
SUB.L
<ea>,Rx
SUB.L
Dy,<ea>
SUBI.L
#imm,Dx
SUBQ.L
#imm,<ea>
SUBX.L
Dy,Dx
3.3.5.5
Miscellaneous Instruction Execution Times
Opcode
<EA>
CPUSHL
(Ax)
LINK.W
Ay,#imm
2(0/1)
MOVE.L
Ay,USP
3(0/0)
MOVE.L
USP,Ax
3(0/0)
MOVE.W
CCR,Dx
1(0/0)
MOVE.W
<ea>,CCR
1(0/0)
MOVE.W
SR,Dx
1(0/0)
Freescale Semiconductor
Rn
(An)
(An)+
1(0/0)
3(1/0)
3(1/0)
1(0/0)
—
—
20(0/0)
23(1/0)
23(1/0)
20(0/0)
23(1/0)
23(1/0)
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
1(0/0)
3(1/1)
3(1/1)
1(0/0)
—
—
—
1(0/0)
—
1(0/0)
—
—
1(0/0)
—
—
—
—
—
1(0/0)
3(1/0)
3(1/0)
—
3(1/1)
3(1/1)
1(0/0)
—
—
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
1(0/0)
3(1/0)
3(1/0)
—
3(1/1)
3(1/1)
1(0/0)
—
—
1(0/0)
3(1/1)
3(1/1)
1(0/0)
—
—
Table 3-16. Miscellaneous Instruction Execution Times
Rn
(An)
(An)+
—
11(0/1)
—
—
—
—
—
—
—
—
—
—
—
—
—
MCF5329 Reference Manual, Rev 3
Effective Address
(d16,An)
(d8,An,Xn*SF)
-(An)
(d16,PC)
(d8,PC,Xn*SF)
3(1/0)
3(1/0)
4(1/0)
—
—
—
23(1/0)
23(1/0)
24(1/0)
23(1/0)
23(1/0)
24(1/0)
—
—
3(1/1)
3(1/1)
4(1/1)
—
—
—
—
1(0/0)
2(0/0)
—
—
—
—
—
—
—
—
—
3(1/0)
3(1/0)
4(1/0)
3(1/1)
3(1/1)
4(1/1)
—
—
—
—
—
3(1/0)
3(1/0)
4(1/0)
3(1/1)
3(1/1)
4(1/1)
—
—
—
3(1/1)
3(1/1)
4(1/1)
—
—
—
Effective Address
-(An)
(d16,An) (d8,An,Xn*SF)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ColdFire Core
xxx.wl
#xxx
3(1/0)
1(0/0)
—
—
23(1/0)
20(0/0)
23(1/0)
20(0/0)
—
—
—
—
3(1/1)
—
—
—
1(0/0)
—
—
1(0/0)
—
1(0/0)
—
1(0/0)
3(1/0)
1(0/0)
3(1/1)
—
—
—
—
—
—
—
3(1/0)
1(0/0)
3(1/1)
—
—
—
3(1/1)
—
—
—
xxx.wl
#xxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1(0/0)
—
—
—
3-27