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Pulse-Width Modulation (PWM) Module
Field
3
Reserved, must be cleared.
2–0
Clock A prescaler select. These three bits control the rate of Clock A, which can be used for PWM channels 1 and 5.
PCKA
26.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains four control bits for the selection of center-aligned outputs or left-aligned
outputs for each PWM channel. Write these bits only when the corresponding channel is disabled. See
Section 26.3.2.5, "Left-Aligned Outputs"
detailed description of the PWM output modes.
Address: 0xFC09_0024 (PWMCAE)
7
R
CAE7
W
Reset:
0
Figure 26-6. PWM Center Align Enable Register (PWMCAE)
Field
7,5,3,1
Center align enable for channel n. The even-numbered channels' center align enable has no effect when the
CAEn
corresponding PWMCTL[CONn(n+1)] bit is set. For example, if PWMCTL[CON01] equals 1, PWMCAE[CAE0] has
no affect.
0 Channel n operates in left-aligned output mode
1 Channel n operates in center-aligned output mode
6,4,2,0
Reserved, must be cleared.
26.2.6
PWM Control Register (PWMCTL)
The PWMCTL register provides various control of the PWM module. Change the CONn(n+1) bits only
when both corresponding channels are disabled. See
more detailed description of the concatenation function.
26-6
Table 26-5. PWMPRCLK Field Descriptions (continued)
PCKA
000
001
...
111
and
Section 26.3.2.6, "Center-Aligned Outputs"
6
5
0
CAE5
0
0
Table 26-6. PWMCAE Field Descriptions
MCF5329 Reference Manual, Rev 3
Description
Clock A Rate
Internal bus clock ÷ 2
0
Internal bus clock ÷ 2
1
...
Internal bus clock ÷ 2
7
4
3
2
0
0
CAE3
0
0
0
Description
Section 26.3.2.7, "PWM 16-Bit Functions"
for a more
Access: User Read/Write
1
0
0
CAE1
0
0
for a
Freescale Semiconductor
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