Freescale Semiconductor MCF5329 Reference Manual page 288

Interrupt Controller Modules
appropriate vector number. As the interrupt acknowledge read performs, the vector number returns to the
core. The contents of the CLMASK register load into the SLMASK register, and the CLMASK register
updates to the level of the acknowledge interrupt. Additionally, the processor raises the interrupt mask in
the status register (SR[I]) to match the level of the acknowledged request. At the end of the core's
exception processing, control passes to the interrupt service routine (ISR), shown as the beginning of
segment C.
During C, the initial portion of the ISR executes. Near the end of this segment, the ISR accesses the
peripheral to negate the interrupt request source. At the conclusion of segment C, the SR[I] field can be
lowered to re-enable interrupts with a priority greater than the original request.
The bulk of the interrupt service routine executes in segment D, with interrupts enabled. Near the end of
the service routine, the SR[I] field is again raised to the original acknowledged level, preparing to perform
the context switch.
At the end of segment E, the original value in the saved level mask (SLMASK) is restored in the current
level mask (CLMASK). Optionally, the service routine can directly load the CLMASK register with any
value with pending interrupt requests of certain levels need to be examined.
In segment F, the interrupt service routine completes execution. During this period of time, it is possible
to access the interrupt controller with a software IACK to see if there are any pending properly-enabled
requests. Checking for any pending interrupt requests at this time provides ability to initiate processing of
another interrupt without the need to return from the original and incur the overhead of another interrupt
exception.
At the conclusion of segment G, the processor core returns to the original interrupted task or a different
task ready to execute.
Obviously, there are many variations to the managing of the SR[I] and the CLMASK values to create a
flexible, responsive system for managing interrupt requests within the device.
MCF5329 Reference Manual, Rev 3
14-20 Freescale Semiconductor