Freescale Semiconductor MCF5329 Reference Manual page 332

Enhanced Direct Memory Access (eDMA)
from the TCD local memory at the end of channel execution, therefore allowing software to enable either
feature during channel execution.
Because software can change the configuration during execution, a coherency sequence must be followed.
Consider the scenario the user attempts to execute a dynamic channel link by enabling the
TCDn_CSR[MAJOR_E_LINK] bit as the eDMA engine retires the channel. The
TCDn_CSR[MAJOR_E_LINK] would be set in the programmer's model, but it would be indeterminate
whether the actual link was made before the channel retired.
The following coherency sequence is recommended when executing a dynamic channel link or dynamic
scatter/gather request:
1. Set the TCDn_CSR[MAJOR_E_LINK] bit.
2. Read back the TCDn_CSR[MAJOR_E_LINK] bit.
3. Test the TCDn_CSR[MAJOR_E_LINK] request status.
a) If the bit is set, the dynamic link attempt was successful.
b) If the bit is cleared, the attempted dynamic link did not succeed, the channel was already
retiring.
This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the
TCD local memory controller forces the TCDn_CSR[MAJOR_E_LINK] and TCDn_CSR[E_SG] bits to
zero on any writes to a TCDn after the TCDn_CSR[DONE] bit for that channel is set, indicating the major
loop is complete.
Software must clear the TCDn_CSR[DONE] bit before writing the
TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits. The
TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after
a channel begins execution.
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NOTE
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor