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System Control Module (SCM)
Field
31–0
Contains the data associated with the faulting access of the last internal bus write access. The register contains the
CFDTR
data value taken directly from the write data bus.
11.3
Functional Description
11.3.1
Access Control
The SCM supports the traditional model of two privilege levels: supervisor and user. Typically, memory
references with the supervisor attribute have total accessibility to all the resources in the system, while user
mode references cannot access system control and configuration registers. In many systems, the operating
system executes in supervisor mode, while application software executes in user mode.
The SCM further partitions the access control functions into two parts: one control register defines the
privilege level associated with each bus master (MPR), and another set of control registers define the
access levels associated with the peripheral modules (PACRx).
Each bus transaction targeted for the peripheral space is first checked to see if its privilege rights allow
access to the given memory space. If the privilege rights are correct, the access proceeds on the internal
bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately
aborted and terminated with an exception, and the targeted module not accessed.
11.3.2
Core Watchdog Timer
The core watchdog timer (CWT) prevents system lockup if the software becomes trapped in a loop with
no controlled exit or if a bus transaction becomes hung. The core watchdog timer can be enabled through
CWCR[CWE]; it is disabled at reset. If enabled, the CWT requires the periodic execution of a core
watchdog servicing sequence. If this periodic servicing action does not occur, the timer expires and,
depending on the setting of CWCR[CWRI], different events may occur:
1. An interrupt may be generated to the core.
2. An immediate system reset.
3. Upon the first time-out, a watchdog timer interrupt is asserted. If this time-out condition is not
serviced before a second time-out occurs, the CWT asserts a system reset. This configuration
supports a more graceful response to watchdog time-outs.
4. In addition to these three basic modes of operation, the CWT also supports a windowed mode of
operation. In this mode, the time-out period is divided into four equal segments and the entire
service sequence of the CWT must occur during the last segment (last 25% of the time-out period).
If the timer is serviced anytime (any write to the CWSR register) in the first 75% of the time-out
period, an immediate system reset occurs.
To prevent the core watchdog timer from interrupting or resetting, the CWSR register must be serviced by
performing the following sequence:
1. Write 0x55 to CWSR.
11-14
Table 11-14. CFDTR Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor
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