Freescale Semiconductor MCF5329 Reference Manual page 281

Table 14-15. Interrupt Source Assignment For INTC0 (continued)
Source Module Flag
2
30 I C I2SR[IIF]
31 QSPI QIR register
32 DTIM0 DTER0 register
33 DTIM1 DTER1 register
34 DTIM2 DTER2 register
35 DTIM3 DTER3 register
36 EIR[TXF]
37 EIR[TXB]
38 EIR[UN]
39 EIR[RL]
40 EIR[RXF]
41 EIR[RXB]
42 FEC EIR[MII]
43 EIR[LC]
44 EIR[HBERR]
45 EIR[GRA]
46 EIR[EBERR]
47 EIR[BABT]
48 EIR[BABR]
49–61
62 SCM SCMIR[CFEI]
63
Freescale Semiconductor
Source Description
2
I C Interrupt
QSPI interrupt
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Transmit frame interrupt
Transmit buffer interrupt
Transmit FIFO underrun
Collision retry limit
Receive frame interrupt
Receive buffer interrupt
MII interrupt
Late collision
Heartbeat error
Graceful stop complete
Ethernet bus error
Babbling transmit error
Babbling receive error
Not Used
Core bus error interrupt
Not Used
MCF5329 Reference Manual, Rev 3
Interrupt Controller Modules
Flag Clearing Mechanism
Write I2SR[IIF] = 0
Write 1 to appropriate QIR bit
Write 1 to appropriate DTER0 bit
Write 1 to appropriate DTER1 bit
Write 1 to appropriate DTER2 bit
Write 1 to appropriate DTER3 bit
Write EIR[TXF] = 1
Write EIR[TXB] = 1
Write EIR[UN] = 1
Write EIR[RL] = 1
Write EIR[RXF] = 1
Write EIR[RXB] = 1
Write EIR[MII] = 1
Write EIR[LC] = 1
Write EIR[HBERR] = 1
Write EIR[GRA] = 1
Write EIR[EBERR] = 1
Write EIR[BABT] = 1
Write EIR[BABR] = 1
Write SCMIR[CFEI] = 1
14-13