Freescale Semiconductor MCF5329 Reference Manual page 887

Address
UART0
UART1
UART2
0xFC06_0034 UART Input Port Register (UIPn)
0xFC06_4034
0xFC06_8034
0xFC06_0038 UART Output Port Bit Set Command Register (UOP1n)
0xFC06_4038
0xFC06_8038
0xFC06_003C UART Output Port Bit Reset Command Register (UOP0n)
0xFC06_403C
0xFC06_803C
1
UMR1n, UMR2n, and UCSRn must be changed only after the receiver/transmitter is issued a software reset command. If
operation is not disabled, undesirable results may occur.
2
Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register
contents may also be changed.
Address
DMA Timer 0
DMA Timer 1
DMA Timer 2
DMA Timer 3
0xFC07_0000 DMA Timer n Mode Register (DTMRn)
0xFC07_4000
0xFC07_8000
0xFC07_C000
0xFC07_0002 DMA Timer n Extended Mode Register (DTXMRn)
0xFC07_4002
0xFC07_8002
0xFC07_C002
0xFC07_0003 DMA Timer n Event Register (DTERn)
0xFC07_4003
0xFC07_8003
0xFC07_C003
0xFC07_0004 DMA Timer n Reference Register (DTRRn)
0xFC07_4004
0xFC07_8004
0xFC07_C004
Freescale Semiconductor
Table A-15. UART Module Memory Map (continued)
Register
Table A-16. DMA Timer Module Memory Map
Register
MCF5329 Reference Manual, Rev 3
Register Memory Map Quick Reference
Width
Access Reset Value Section/Page
(bit)
8 R 0xFF
2
8 W 0x00
2
8 W 0x00
Width
Access Reset Value
(bits)
16 R/W 0x0000
8 R/W 0x00
8 R/W 0x00
32 R/W 0xFFFF_FFFF
31.3.12/31-15
31.3.13/31-16
31.3.13/31-16
Section/Page
29.2.1/29-3
29.2.2/29-4
29.2.3/29-5
29.2.4/29-6
A-11