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DMA references in this section refer to the FEC's DMA engine. This DMA
engine transfers FEC data only and is not related to the eDMA controller
described in
to the DMA timers described in
(DTIM0–DTIM3)."
The RAM is the focal point of all data flow in the Fast Ethernet controller and divides into transmit and
receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from
the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the
transmit block, and receive data flows from the receive block into the receive FIFO.
You control the FEC by writing into control registers located in each block. The CSR (control and status
registers) block provides global control (Ethernet reset and enable) and interrupt managing registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the FEC_MDC (management data clock) and
FEC_MDIO (management data input/output) lines of the MII interface.
The FEC DMA block (not to be confused with the device's eDMA controller) provides multiple channels
allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run
independently.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The message information block (MIB) maintains counters for a variety of network events and statistics. It
is not necessary for operation of the FEC, but provides valuable counters for network management. The
counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3
counters. See
Section 19.4.1, "MIB Block Counters Memory Map,"
19.1.3
Features
The FEC incorporates the following features:
•
Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
•
IEEE 802.3 full duplex flow control
•
Programmable max frame length supports IEEE 802.1 VLAN tags and priority
•
Support for full-duplex operation (200 Mbps throughput) with a minimum internal bus clock rate
of 50 MHz
•
Support for half-duplex operation (100 Mbps throughput) with a minimum internal bus clock rate
of 50 MHz
•
Retransmission from transmit FIFO following a collision (no processor bus utilization)
Freescale Semiconductor
NOTE
Chapter 16, "Enhanced Direct Memory Access (eDMA),"
Chapter 29, "DMA Timers
MCF5329 Reference Manual, Rev 3
Fast Ethernet Controller (FEC)
nor
for more information.
19-3
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