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Liquid Crystal Display Controller (LCDC)
Field
31–8
Reserved, must be cleared.
7
Graphic window underrun error interrupt enable.
GWUDR
0 Mask interrupt.
1 Enable interrupt.
6
Graphic window error response interrupt enable.
GWERR
0 Mask interrupt.
1 Enable interrupt.
5
Graphic window end-of-frame interrupt enable.
GWEOF
0 Mask interrupt.
1 Enable interrupt.
4
Graphic window beginning-of-frame interrupt enable.
GWBOF
0 Mask interrupt.
1 Enable interrupt.
3
Underrun error interrupt enable.
UDR
0 Mask interrupt.
1 Enable interrupt.
2
Error response interrupt enable.
ERR
0 Mask interrupt.
1 Enable interrupt.
1
End-of-frame interrupt enable.
EOF
0 Mask interrupt.
1 Enable interrupt.
0
Beginning-of-frame interrupt enable.
BOF
0 Mask interrupt.
1 Enable interrupt.
22.3.17 LCDC Interrupt Status Register (LCD_ISR)
The read-only interrupt status register indicates whether an interrupt has occurred. The status bit is set
when the interrupt condition is met. If any bit in this register is set and the corresponding bit in the
LCD_IER register is set, an LCD interrupt is asserted to the interrupt controller. The status bit is cleared
by reading the register.
22-20
Table 22-19. LCD_IER Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor
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