Pll Feedback Divider Register (Pfdr) - Freescale Semiconductor MCF5329 Reference Manual

Clock Module
Field
7–0 Dither modulation divider.
Dither Modulation Frequency = Input Frequency / (MODDIV × 32)
MODDIV
A dither modulation frequency greater than 105 kHz or less than 9.95 kHz is invalid. For example, for a 16 MHz input
frequency, MODDIV may be programmed between 5 (100 kHz) and 50 (10 kHz). Programming MODDIV outside
the specified range results in unpredictable PLL operation.
Note: This field should only be written when dithering mode is disabled (PCR[DITHEN] = 0). Else, unpredictable PLL
operation results.
7.2.4

PLL Feedback Divider Register (PFDR)

Address: 0xFC0C_000C (PFDR)
7
R
W
Reset: See Note
Note: Reset value determined by reset configuration. See
more information. For the default reset configuration (RCON negated), the reset value is 0x5A. If RCON
and D1 is asserted at reset, the reset value of PFDR is 0x78.
Field
7–0 The MFD bits control the value of the divider in the PLL feedback loop. The value specified by the MFD bits establish
MFD the multiplication factor applied to the reference frequency. See
Select" for more details.
0x58 88
0x59 89
0x5A 90
...
0x86 134
0x87 135
Else Reserved
Note: The MFD bits may only be written when the device is in limp mode (MISCCR[LIMP] = 1).
7.3 Functional Description
This subsection provides a functional description of the clock module.
7.3.1 PLL Dithered and Non-Dithered Operation
The PLL is capable of generating output clocks with a frequency that modulates in a triangular waveform
with a specified percentage frequency deviation and a specified dither modulation frequency. This
modulation of the output clock is called dithered operation. When the PLL operates at a fixed frequency,
7-8
Table 7-5. PMDR Field Descriptions
6 5
See Note See Note See Note
Figure 7-6. PLL Feedback Divider Register (PFDR)
Table 7-6. PFDR Field Descriptions
MCF5329 Reference Manual, Rev 3
Description
4 3 2
MFD
See Note See Note
Chapter 9, "Chip Configuration Module (CCM),"
Description
Section 7.3.3, "PLL Frequency Multiplication Factor
Access: User read/write
1 0
See Note See Note
for
Freescale Semiconductor