Freescale Semiconductor MCF5329 Reference Manual page 211

Slot Number
The PACRn field is defined as shown below.
Field
3 Reserved, should be cleared.
2 Supervisor protect. Determines whether the peripheral requires supervisor privilege level for access.
SP 0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate
supervisor access attribute, and the MPROTn[MPL] control bit for the master must be set. If not, the access is
terminated with an error response and no peripheral access is initiated.
1 Write protect. Determines whether the peripheral allows write accesses
WP 0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, the access is terminated with an error response
and no peripheral access is initiated.
0 Trusted Protect. Determines whether the peripheral allows accesses from an untrusted master.
TP 0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access
is terminated with an error response and no peripheral access is initiated.
11.2.4 Bus Monitor Timeout Registers (BMTn)
Each AIPS controller implements a bus timeout monitor to insure that every bus cycle is properly
terminated within a programmed period of time. The monitor continually checks for termination of each
bus cycle and completes the cycle if there is no response when the programmed monitor cycle count is
reached.
The monitor can be programmed from 8–1024 internal bus cycles under control of the BMT register. If the
programmed timeout value is reached before a termination, the bus monitor completes the cycle with an
error termination. Thus, the SCMISR[CFEI] bit is set, and an interrupt to the interrupt controller is
generated if the CFIER[ECFEI] bit is set. At reset, the BMT is enabled with a maximum timeout value.
Freescale Semiconductor
Table 11-4. PACRn Assignments (continued)
PACRn
47 PACR47
48 PACR48
56 PACR56
57 PACR57
58 PACR58
3
R 0
W
Figure 11-12. PACRn Fields
Table 11-5. PACRn Field Descriptions
MCF5329 Reference Manual, Rev 3
Peripheral
SSI
PLL
MDHA
SKHA
RNG
2 1 0
SP WP TP
Description
System Control Module (SCM)
11-7