Freescale Semiconductor MCF5329 Reference Manual page 370

SDRAM Controller (SDRAMC)
Table 18-3. SDRAM Address Multiplexing in 32-bit Bus Mode (continued)
Device Configuration
32M x 32 bit
1 Gbits
64M x 16 bit
2 Gbits 64M x 32 bit
1
All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown.
2
All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an
extra bit CA10 to control the precharge option.
SDCR[ADDR_MUX]
Table 18-5. SDRAM-Address Multiplexing in 16-bit Bus Mode
Device Configuration
4M x 16 bit
8M x 8 bit
64 Mbits
16M x 4 bit
18-8
Row bit x SDCR
Col bit x [ADDR_
Banks MUX] 27
12 x 11 x 4 00 —
13 x 10 x 4 01 —
14 x 9 x 4 10 —
12 x 12 x 4 00 CA12
13 x 11 x 4 01 CA11
14 x 10 x 4 10 CA9
12 x 12 x 4 00 CA12
13 x 11 x 4 01 CA11
14 x 10 x 4 10 CA9
Table 18-4. Address Multiplexing for 16-bit Bus Mode
Internal Address Bits [27:24]
IA[27]
00 CA13
01 CA12
10 CA11
11
Row bit x SDCR
Col bit x [ADDR_
Banks MUX] 27
1,2
11 x 9 x 4 00 —
12 x 9 x 4 00 —
12 x 10 x 4 00 —
13 x 9 x 4 01 —
MCF5329 Reference Manual, Rev 3
Internal Address
26 25 24
CA11 CA9 CA8
CA9 CA8 RA12
CA8 RA13 RA12
CA11 CA9 CA8
CA9 CA8 RA12
CA8 RA13 RA12
CA11 CA9 CA8
CA9 CA8 RA12
CA8 RA13 RA12
IA[26] IA[25]
CA12 CA11
CA11 CA9
CA9 RA13
Reserved. Do Not Use.
Internal Address
26 25 24
— — —
— — —
— — CA9
— — RA12
23–12 11–10 9–2
RA11-0 BA1-0 CA7-0
RA11-0 BA1-0 CA7-0
IA[24]
CA9
RA12
RA12
23 – 12 11 – 10 9 – 1
RA11-0 BA1-0 CA8-0
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