Freescale Semiconductor MCF5329 Reference Manual page 96

ColdFire Core
Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.
BDM: Load: 0x081 (D1)
Store: 0x181 (D1)
31 30 29
R CLSZ 0
W
Reset 0 0 0
15 14 13
R MBSZ UCAS
W
Reset 0 0 0
Table 3-10. D1 Hardware Configuration Information Field Description
Field
31–30 Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
CLSZ
29–24 Reserved.
23–16 Reserved.
15–14 Bus size. Defines the width of the ColdFire master bus datapath.
MBSZ 00 32-bit system bus datapath (This is the value used for this device)
01 64-bit system bus datapath
Else Reserved
13–12 Unified cache associativity. Defines the unified cache set-associativity.
UCAS 00 Four-way (This is the value used for this device)
01 Direct mapped
Else Reserved for future use
11–8 Unified cache size. Indicates the size of the unified cache.
UCSZ 0000 No unified cache
0001 512 bytes
0010 1 Kbytes
0011 2 Kbytes
0100 4 Kbytes
0101 8 Kbytes
0110 16 Kbytes (This is the value used for this device)
0111 32 Kbytes
Else Reserved for future use
3-22
28 27 26 25
0 0 0 0
0 0 0 0
12 11 10 9
UCSZ
0 0 1 1
Figure 3-14. D1 Hardware Configuration Info
MCF5329 Reference Manual, Rev 3
24 23 22 21
0 0 0 0
0 0 0 0
8 7 6 5
SRAMSZ
0 0 1 1
Description
Access: User read-only
BDM read-only
20 19 18 17
0 0 0 0
0 0 0 0
4 3 2 1
0 0
1 0 0 0
Freescale Semiconductor
16
0
0
0
0
0