Table of Contents
Advertisement
Field
1
Initiate precharge all command. Used to force a software-initiated precharge all command. This bit is write-only,
IPALL
reads return zero.
0 Do not generate a precharge command.
1 Generate a precharge all command. All SD_CSn signals are asserted simultaneously. SDCR[CKE] must be
set before generating a software precharge command.
Note: Software precharge is only possible when MODE_EN is set.
Note: Do not set IREF and IPALL at the same time.
0
Reserved, should be cleared.
18.4.3
SDRAM Configuration Register 1 (SDCFG1)
The 32-bit read/write SDRAM configuration register 1 (SDCFG1) stores necessary delay values between
specific SDRAM commands. During initialization, software loads values to the register according to the
selected SD_CLK frequency and SDRAM information obtained from the data sheet. This register resets
only by a power-up reset signal.
The read and write latency fields govern the relative timing of commands and data and must be exact
values. All other fields govern the relative timing from one command to another; they have minimum
values, but any larger value is also legal (but with decreased performance).
The minimum values of certain fields can be different for SDR, DDR SDRAM, even if the data sheet
timing is the same, because:
•
In SDR mode, the memory controller counts the delay in SD_CLK
•
In DDR mode, the memory controller counts the delay in 2 x SD_CLK (also referred to as
SD_CLK2)
•
SD_CLK—memory controller clock—is the speed of the SDRAM interface and is equal to the
internal bus clock.
•
SD_CLK2—double frequency of SD_CLK—DDR uses both edges of the bus-frequency clock
(SD_CLK) to read/write data
In all calculations for setting the fields of this register, convert time units to
clock units and round up to the nearest integer.
Freescale Semiconductor
Table 18-8. SDCR Field Descriptions (continued)
NOTE
MCF5329 Reference Manual, Rev 3
Description
SDRAM Controller (SDRAMC)
18-17
Advertisement
Table of Contents
