Lcd Controller Signals; Ethernet Module (Fec) Signals - Freescale Semiconductor MCF5329 Reference Manual

Signal Name
DMA Request
DMA Acknowledge
2.3.8

LCD Controller Signals

Table 2-9 describes the LCD controller signals.
Signal Name Abbreviation
Line Data LCD_D[17:0]
First Line Marker/ LCD_FLM/
Vertical Sync LCD_VSYNC
Line Pulse/ LCD_LP/
Horizontal Sync LCD_HSYNC
Shift Clock LCD_LSCLK
Alt. Crystal Direction/ LCD_ACD/
Output Enable LCD_OE
Contrast LCD_CONTRAST Controls the LCD bias voltage for contrast control.
Power Save LCD_PS
Gate Driver Clock LCD_CLS
Signal
Reverse Control LCD_REV
Sampling Start Signal LCD_SPL_SPR
2.3.9

Ethernet Module (FEC) Signals

The following signals are used by the Ethernet module for data and clock signals.
Signal Name
Management Data
Management Data
Clock
Freescale Semiconductor
Table 2-9. DMA Signals
Abbreviation
DREQ[1:0] Active low external DMA request lines.
DACK[1:0] Active low external DMA acknowledge lines.
Table 2-10. LCD Signals
LCD data bus.
Passive matrix: First line marker
Active matrix: Vertical sync pulse. Indicates start of next frame.
Passive matrix: Line pulse
Active matrix: Horizontal sync pulse. Indicates start of next line.
Clock for latching data into the display driver's internal shift register.
Passive matrix: Alternate crystal direction
Active matrix: Output enable to enable data to be shifted onto the display.
Controls signal output for source driver (Sharp HR-TFT 240x320 panels
only)
Start signal output for gate driver, inverted version of LCD_PS (Sharp
HR-TFT 240x320 panels only).
Signal for common electrode driving signal preparation (Sharp HR-TFT
240x320 panels only).
Sets the horizontal scan direction (Sharp HR-TFT 240x320 panels only).
Table 2-11. Ethernet Module (FEC) Signals
Abbreviation
FEC_MDIO Transfers control information between the external PHY and the
media-access controller. Data is synchronous to FEC_MDC. Applies
to MII mode operation. This signal is an input after reset. When the
FEC is operated in 10Mbps 7-wire interface mode, this signal should
be connected to VSS.
FEC_MDC In Ethernet mode, FEC_MDC is an output clock which provides a
timing reference to the PHY for data transfers on the FEC_MDIO
signal. Applies to MII mode operation.
MCF5329 Reference Manual, Rev 3
Function
Function
Function
Signal Descriptions
I/O
I
O
I/O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
O
2-13