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Pulse-Width Modulation (PWM) Module
Field
7–0
Current value of the PWM up counter. Resets to zero when written.
COUNT
26.2.10 PWM Channel Period Registers (PWMPERn)
The PWM period registers determine the period of the associated PWM channel. Refer to
"PWM Period and Duty"
Calculating the output period depends on the output mode (center-aligned has twice the period as
left-aligned mode) as well as PWMPERn. See the below equation:
PWMn period
For boundary case programming values (e.g. PWMPERn = 0x00), please refer to
Boundary
Cases".
Address: 0xFC09_0034 (PWMPER0)
0xFC09_0035 (PWMPER1)
0xFC09_0036 (PWMPER2)
0xFC09_0037 (PWMPER3)
0xFC09_0038 (PWMPER4)
0xFC09_0039 (PWMPER5)
0xFC09_003A (PWMPER6)
0xFC09_003B (PWMPER7)
7
R
W
Reset:
1
Field
7–0
Period counter for the output PWM signal.
PERIOD
If PERIOD equals 0x00, the PWMn output is always high (PPOLn=1) or always low (PPOLn=0). See
Section 26.3.2.8, "PWM Boundary Cases"
26.2.11 PWM Channel Duty Registers (PWMDTYn)
The PWM duty registers determine the duty cycle of the associated PWM channel. To calculate the output
duty cycle (high time as a percentage of period) for a particular channel:
Duty Cycle
26-10
Table 26-10. PWMCNTn Field Descriptions
for more information.
×
(
=
Channel clock period
PWMCAE CAEn
6
5
1
1
Figure 26-11. PWM Period Registers (PWMPERn)
Table 26-11. PWMPERn Field Descriptions
for other special cases.
⎛
[
=
1 PWMPOL PPOLn
–
⎝
MCF5329 Reference Manual, Rev 3
Description
[
]
)
×
+
1
PWMPERn
4
3
2
PERIOD
1
1
1
Description
⎞
PWMDTYn
]
×
----------------------------- -
–
100%
⎠
PWMPERn
Section 26.3.2.3,
Eqn. 26-3
Section 26.3.2.8, "PWM
Access: User Read/Write
1
0
1
1
Eqn. 26-4
Freescale Semiconductor
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