Sdram Controller (Sdramc); Introduction - Freescale Semiconductor MCF5329 Reference Manual

Chapter 18

SDRAM Controller (SDRAMC)

18.1

Introduction

This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It
begins with a general description and brief glossary and includes a description of signals involved in
DRAM operations. The remainder of the chapter describes the programming model and signal timing, as
well as the command set required for synchronous operations. It also includes examples to better
understand how to configure the DRAM controller for synchronous operations.
Unless otherwise noted, in this chapter clock refers to the system clock
(f ).
sys/3
The external data bus is shared between the FlexBus module and the
SDRAM controller. When the SDRAM controller is in SDR mode
(DRAMSEL = 1), the data bus is switched dynamically between the
SDRAM controller and the FlexBus module. However, when the SDRAM
controller is in DDR mode (DRAMSEL = 0), D[31:16] is dedicated to the
SDRAM data bus and D[15:0] is dedicated to the FlexBus data bus.
In this chapter, the SDRAM data bus signals are named SD_D[31:0].
However, because these signals share external pins with the FlexBus, the
pin names on the device are D[31:0].
Freescale Semiconductor
NOTE
MCF5329 Reference Manual, Rev 3
18-1