Freescale Semiconductor MCF5329 Reference Manual page 734

UART Modules
True status is provided in the UISRn regardless of UIMRn settings. UISRn
is cleared when the UART module is reset.
Address: 0xFC06_0014 (UISR0)
0xFC06_4014 (UISR1)
0xFC06_8014 (UISR2)
7
R
COS
(UISRn)
W
COS
(UIMRn)
Reset: 0
Figure 31-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
Field
7 Change-of-state.
COS 0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on UnCTS and was programmed in UACRn[IEC] to cause an interrupt.
6–3 Reserved, must be cleared.
2 Delta break.
DB 0 No new break-change condition to report.
-
RESET BREAK CHANGE INTERRUPT
1 The receiver detected the beginning or end of a received break.
1 Status of FIFO or receiver, depending on UMR1[FFULL/RXRDY] bit. Duplicate of USRn[FIFO] and USRn[RXRDY]
FFULL/
RXRDY
[FFULL/RXRDY]
0 Transmitter ready. This bit is the duplication of USRn[TXRDY].
TXRDY 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the
transmitter holding register when TXRDY is cleared are not sent.
1 The transmitter holding register is empty and ready to be loaded with a character.
31-14
NOTE
6 5
0 0
0 0
0 0
Table 31-10. UISRn/UIMRn Field Descriptions
Section 31.3.5, "UART Command Registers
command.
UIMRn UISRn
[FFULL/RXRDY]
0 0
1 0
0 1
1 1
MCF5329 Reference Manual, Rev 3
4 3 2
0 0 DB
0 0 DB
0 0 0
Description
UMR1n[FFULL/RXRDY]
0 (RXRDY)
Receiver not ready
Receiver not ready
Receiver is ready,
Do not interrupt
Receiver is ready,
interrupt
Access: User read/write
1 0
FFULL/
TXRDY
RXRDY
FFULL/
TXRDY
RXRDY
0 0
(UCRn)," describes the
1 (FIFO)
FIFO not full
FIFO not full
FIFO is full,
Do not interrupt
FIFO is full,
interrupt
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