Freescale Semiconductor MCF5329 Reference Manual page 910

Revision History
Table B-2. MCF5329RM Rev 1 to Rev. 2 Changes (continued)
Chapter
FlexBus Rearranged sections for consistency.
Section 17.4.4 & 17.4.5: In figure 17-8 through figure 17-33 add ADDR[31:0] label to first cycle of data signals.
Section 17.4.4.1/Page 17-12: Change last note on page from
to:
Figure 17-27/Page 17-24: Remove internal termination dashed lines for FB_CS, FB_BE/BWE, and FB_OE
signals.
Figure 17-31/Page 17-26: Remove internal termination dashed lines for FB_CS, FB_BE/BWE, and FB_OE
signals.
Figure 17-33/Page 17-27: Remove internal termination dashed lines for FB_CS, FB_BE/BWE, and FB_OE
signals.
SDRAM Changed SD_VREF signal description.
Controller
Clarified series termination and SD_CLK termination in DDR layout considerations.
Clarified DDR SDRAM termination circuit example figure.
Corrected typos in SDCR[DQS_OE] bit description: from DSQ to DQS.
Table 18-1/Page 18-5: In the SD_DQS table entry add the following note:
Note: If a read is attempted from a DDR SDRAM chip select when there is no memory to respond with the
appropriate SD_DQS pulses, the bus cycle hangs. Because there is no high level bus monitor on the device, a
reset is the only way to exit this error condition.
Figure 18-2/Page 18-11: Replace figure with Figure 1 from AN2982 "System Design Using the ColdFire
MCF5208 Split Bus Architecture" found at
Figure 18-2/Page 18-12: SD_D[31:0], DQ[31:0], SD_DQS[3:0], and DQS[3:0] should be SD_D[31:16],
DQ[31:16], SD_DQS[3:2], and DQS[3:2], respectively, as the device does not support a 32-bit DDR bus.
Replace figure with Figure 2 from AN2982 "System Design Using the ColdFire MCF5208 Split Bus Architecture"
found at http://www.freescale.com/coldfire
Section 18.3.5/Page 18-13: Remove this entire section, as the device does not support a 32-bit wide DDR bus.
Table 18-8/Page 18-17: DQS_OE field should match the corresponding register diagram and be only 2 bits wide
at locations 11–10. Change third sentence from "The DSQ_OE[3] bit enables SD_DQS3 and the DSQ_OE[2]
bit enables SD_DQS2, and so on." to ""The DSQ_OE[1] bit enables SD_DQS3 and the DSQ_OE[0] bit
enables SD_DQS2."
Consequently, the reserved bit field currently at location 7–3 should be extended to bits 9–3.
B-8
Description
"The processor drives the data lines during the first clock cycle of the
transfer. However, this should be ignored by the connected device."
"The processor drives the data lines during the first clock cycle of the
transfer with the full 32-bit address. This may be ignored by standard
connected devices using non-multiplexed address and data buses.
However, some applications may find this feature beneficial."
http://www.freescale.com/coldfire
because it is more thorough.
MCF5329 Reference Manual, Rev 3
because it is more thorough.
Freescale Semiconductor