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where f
is the core frequency. The allowable range of values for the PFDR is 88 to 135, resulting in a
sys
frequency multiplication factor range of 11 to 16.88 times the input reference frequency (typically
16 MHz).
The PFDR can only be modified while the device is in limp mode, which is entered by setting the
MISCCR[LIMP] bit. After the PFDR register has been changed, re-enter normal mode by clearing the
MISCCR[LIMP] bit. The PLL then begins to acquire lock accordingly on the new frequency.
7.3.4
System Clock Modes
The system clock source is determined during reset. By default the PLL is placed in crystal reference mode
and generates a core/bus frequency of 180/60 MHz. This default mode can be overridden by asserting the
RCON pin. See
Chapter 9, "Chip Configuration Module (CCM),"
default configuration during reset.
Table 7-7
shows the clock-out frequency to clock-in frequency relationships for the possible system clock
modes. Refer to
Section 7.1.3, "Modes of Operation"
System Clock Mode
Normal PLL clock mode
Limp mode
1
f
= input reference frequency = 16 MHz
ref
PFDR ranges from 88 to 135
MISCCR[LPDIV] ranges from 0 to 15
7.3.5
Clock Operation During Reset
This section describes the reset operation of the PLL. Power-on reset and normal reset are described.
7.3.5.1
Power-On Reset (POR)
After V
and the input clock are within specification, the PLL is held in reset for at least 10 input
DDPLL
clock cycles to initialize the PLL. The reset configuration signals are used to select the multiply factor of
the PLL and the reset state of the PLL registers. While in reset, the PLL input clock is output to the device.
After RESET is de-asserted, PLL output clocks are generated; however, until the MISCCR[PLLLOCK]
bit is set the PLL output clock frequencies are not stable and not within specification. The
MISCCR[PLLLOCK] bit is set after RESET has negated for a minimum of 1 ms. When this bit is set, the
PLL is in frequency lock.
Freescale Semiconductor
Table 7-7. Clock Out and Clock In Relationships
1
PLL Options
⎛
⎞
PFDR
×
--------------- -
f
=
f
⎝
⎠
sys
ref
8
f
ref
-----------------------------------------
f
=
[
sys
MISCCR LPDIV
2
MCF5329 Reference Manual, Rev 3
for more information on overriding the
for details on each mode.
Cross-Reference
Section 7.1.3.1, "Normal PLL Mode with
Crystal Reference"
and
"Normal PLL Mode with External Reference"
Section 7.1.3.3, "Input Clock (Limp) Mode"
]
Clock Module
Section 7.1.3.2,
7-11
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