Freescale Semiconductor MCF5329 Reference Manual page 686

Programmable Interrupt Timers (PIT0–PIT3)
The low-power interrupt control register (LPICR) in the system control
module specifies the interrupt level at or above which the device can be
brought out of a low-power mode.
Low-power Mode
Wait
Doze
Stop
Debug
In wait mode, the PIT module continues to operate as in run mode and can be configured to exit the
low-power mode by generating an interrupt request. In doze mode with the PCSRn[DOZE] bit set, PIT
module operation stops. In doze mode with the PCSRn[DOZE] bit cleared, doze mode does not affect PIT
operation. When doze mode is exited, PIT continues operating in the state it was in prior to doze mode. In
stop mode, the internal bus clock is absent and PIT module operation stops.
In debug mode with the PCSRn[DBG] bit set, PIT module operation stops. In debug mode with the
PCSRn[DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is exited, the PIT
continues to operate in its pre-debug mode state, but any updates made in debug mode remain.
28.2 Memory Map/Register Definition
This section contains a memory map (see
Longword accesses to any of the programmable interrupt timer registers
results in a bus error. Only byte and word accesses are allowed.
Table 28-2. Programmable Interrupt Timer Modules Memory Map
Address
PIT 0
PIT 1
PIT 2
PIT 3
0xFC08_0000 PIT Control and Status Register (PCSRn)
0xFC08_4000
0xFC08_8000
0xFC08_C000
28-2
NOTE
Table 28-1. PIT Module Operation in Low-power Modes
PIT Operation
Normal
Normal if PCSRn[DOZE] cleared,
stopped otherwise
Stopped
Normal if PCSRn[DBG] cleared,
stopped otherwise
Table 28-2) and describes the register structure for PIT0–PIT3.
NOTE
Register
Supervisor Access Only Registers
MCF5329 Reference Manual, Rev 3
Mode Exit
N/A
Any interrupt at or above level in LPICR, exit doze
mode if PCSRn[DOZE] is set. Otherwise
interrupt assertion has no effect.
No
No. Any interrupt is serviced upon normal exit
from debug mode
Width
1
Access Reset Value
(bits)
2
16 R/W 0x0000
Section/Page
28.2.1/28-3
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