Freescale Semiconductor MCF5329 Reference Manual page 241

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329
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Address
0xFC0A_4031 PPDSDR_UART
0xFC0A_4032 PPDSDR_QSPI
0xFC0A_4033 PPDSDR_TIMER
0xFC0A_4035 PPDSDR_LCDDATAH
0xFC0A_4036 PPDSDR_LCDDATAM
0xFC0A_4037 PPDSDR_LCDDATAL
0xFC0A_4038 PPDSDR_LCDCTLH
0xFC0A_4039 PPDSDR_LCDCTLL
0xFC0A_403C PCLRR_FECH
0xFC0A_403D PCLRR_FECL
0xFC0A_403E PCLRR_SSI
0xFC0A_403F PCLRR_BUSCTL
0xFC0A_4040 PCLRR_BE
0xFC0A_4041 PCLRR_CS
0xFC0A_4042 PCLRR_PWM
0xFC0A_4043 PCLRR_FECI2C
0xFC0A_4045 PCLRR_UART
0xFC0A_4046 PCLRR_QSPI
0xFC0A_4047 PCLRR_TIMER
0xFC0A_4049 PCLRR_LCDDATAH
0xFC0A_404A PCLRR_LCDDATAM
0xFC0A_404B PCLRR_LCDDATAL
0xFC0A_404C PCLRR_LCDCTLH
0xFC0A_404D PCLRR_LCDCTLL
0xFC0A_4050 PAR_FEC
0xFC0A_4051 PAR_PWM
0xFC0A_4052 PAR_BUSCTL
0xFC0A_4053 PAR_FECI2C
0xFC0A_4054 PAR_BE
0xFC0A_4055 PAR_CS
Freescale Semiconductor
Table 13-3. GPIO Module Memory Map (continued)
Register
Port Clear Output Data Registers
Pin Assignment Registers
MCF5329 Reference Manual, Rev 3
General Purpose I/O Module
Width
Access Reset Value
(bits)
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0xF8
8
R/W
0x00
8
R/W
0x0F
8
R/W
0x3E
Section/Page
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13.3.5.1/13-24
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13.3.5.2/13-24
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