Performing A Mac Operation With The Macfull Bit - Freescale Semiconductor MCF5329 Reference Manual

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329
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Message Digest Hardware Accelerator (MDHA)
10. MDHA does the required algorithm's auto padding of the message.
11. Set the MDCMR[GO] bit.
12. Wait for MDSR[DONE] to be set or done interrupt to be triggered to indicate successful
completion (or failure).
You need to provide a time-out feature in the interrupt handler. The MDHA
stalls with no response if it is waiting for message data. This most likely
occurs if the MDDSR write is not received or auto-padding is disabled and
a partial message block is provided.
13. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the
message digest registers.
33.4.5

Performing a MAC Operation With the MACFULL Bit

The HMAC/EHMAC is done in one step with the MACFULL bit.
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, HMAC or EHMAC, and MACFULL bits.
4. Direct context load of key into MDx1 registers.
5. MDMDS register write. Load this register with the length of the key.
6. Fill data FIFO with message to be hashed.
7. MDDSR register write. Load this register with the length of the message data (without padding) in
bytes.
8. MDHA does the required algorithm's auto padding of the message.
9. Set the MDCMR[GO] bit.
10. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful completion
(or failure).
You need to provide a time-out feature in the interrupt handler. The MDHA
stalls with no response if it is waiting for message data. This most likely
occurs if the MDDSR write is not received or auto-padding is disabled and
a partial message block is provided.
11. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the
message digest registers.
33.4.6
Performing an NMAC
An NMAC consists of one Hash operation.
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
33-18
NOTE
NOTE
MCF5329 Reference Manual, Rev 3
Freescale Semiconductor

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