Freescale Semiconductor MCF5329 Reference Manual page 759

Field
2
7 I C enable. Controls the software reset of the entire I
IEN transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected.
Master mode is not aware that the bus is busy; initiating a start cycle may corrupt the current bus cycle, ultimately
causing the current master or the I
2
0 The I C module is disabled, but registers can be accessed.
2
1 The I C module is enabled. This bit must be set before any other I2CR bits have any effect.
2
6 I C interrupt enable.
2
IIEN 0 I C module interrupts are disabled, but currently pending interrupt condition is not cleared.
2
1 I C module interrupts are enabled. An I
5 Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal.
MSTA 0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.
4 Transmit/receive mode select bit. Selects the direction of master and slave transfers.
MTX 0 Receive
1 Transmit. When the device is addressed as a slave, software must set MTX according to I2SR[SRW]. In master
mode, MTX must be set according to the type of transfer required. Therefore, when the MCU addresses a slave
device, MTX is always 1.
3 Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during acknowledge cycles for master and
TXAK slave receivers. Writing TXAK applies only when the I
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
1 No acknowledge signal response is sent (acknowledge bit = 1).
2 Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration.
RSTA 0 No repeat start
1 Generates a repeated START condition.
1 Reserved, must be cleared.
2
32.2.4 I C Status Register (I2SR)
I2SR contains bits that indicate transaction direction and status.
Address: 0xFC05_800C (I2SR)
7
R ICF
W
Reset: 1
Freescale Semiconductor
Table 32-4. I2CR Field Descriptions
2
C module to lose arbitration, after which bus operation returns to normal.
2
C interrupt occurs if I2SR[IIF] is also set.
6 5
IAAS IBB
IAL
0 0 0
2
Figure 32-5. I C Status Register (I2SR)
MCF5329 Reference Manual, Rev 3
Description
2
C module. If the module is enabled in the middle of a byte
2
C bus is a receiver.
4 3 2
0 SRW
0 0
2
I C Interface
Access: User read/write
1 0
RXAK
IIF
0 1
32-5