Freescale Semiconductor MCF5329 Reference Manual page 355

In addition to address setup, a programmable address hold option for each chip select exists. Address and
attributes can be held one to four clocks after chip-select, byte-selects, and output-enable negate.
Figure 17-23 and Figure 17-24
FB_CLK
FB_A[23:0]
FB_D[31:X]
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 17-23. Read Cycle with Two-Clock Address Hold (No Wait States)
FB_CLK
FB_A[23:0]
FB_D[31:X]
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 17-24. Write Cycle with Two-Clock Address Hold (No Wait States)
Freescale Semiconductor
show read and write bus cycles with two clocks of address hold.
S0 S1 S2
ADDR[23:0]
ADDR[31:X]
DATA
S0 S1 S2
ADDR[23:0]
DATA
ADDR[31:X]
MCF5329 Reference Manual, Rev 3
AH S3 S0
AH S3 S0
FlexBus
17-23