Test Signals; Power And Ground Pins - Freescale Semiconductor MCF5329 Reference Manual

2.3.19

Test Signals

Table 2-22 describes test signals which are reserved for factory testing.
Signal Name
Test
PLL Test
2.3.20

Power and Ground Pins

The pins described in Table 2-23
for adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
Signal Name
PLL Analog Supply
Positive I/O Supply
Positive Core Supply
SDRAMC Supply
USB Supply
USB Ground
Ground
Freescale Semiconductor
Table 2-21. Processor Status (continued)
PST[3:0]
1001 Begin two-byte transfer on DDATA
1010 Begin three-byte transfer on DDATA
1011 Begin four-byte transfer on DDATA
1100 Exception processing
1101 Reserved
1110 Processor is stopped
1111 Processor is halted
Table 2-22. Test Signals
Abbreviation
TEST Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of test
functions.
PLL_TEST Reserved for factory testing only and should be treated as a
no-connect (NC).
provide system power and ground to the chip. Multiple pins are provided
Table 2-23. Power and Ground Pins
Abbreviation
PLL_VDD Dedicated power supply signals to isolate the sensitive PLL analog
PLL_VSS (VCO) circuitry from the normal levels of noise present on the digital
power supply.
EVDD These pins supply positive power to the I/O pads
IVDD These pins supply positive power to the core logic.
SD_VDD These pins supply positive power to the SDRAM controller.
USB_VDD These pins supply positive power to the USB controllers.
USB_VSS These pins are the negative supply (ground) for the USB controllers.
VSS These pins are the negative supply (ground) for the device.
MCF5329 Reference Manual, Rev 3
Processor Status
Function
Function
Signal Descriptions
I/O
I
O
I/O
—
.
—
—
—
—
—
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2-19