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9.3.4
Miscellaneous Control Register (MISCCR)
The MISCCR register provides clock source selection and configuration for internal clocks, as well as
SSI/timer DMA mux control and other miscellaneous control functionality.
Address: 0xFC0A_0010 (MISCCR)
15
14
13
R
PLL
0
0
LOCK LIMP
W
Reset
0
0
1
1
Reset value depends on RCON RLIMP selection; 0 for PLL operation, 1 for low-power divider operation.
2
Reset value depends on RCON PLLMODE selection; 0 for 180 MHz operation, 1 for 240 MHz operation.
Field
15–14
Reserved, should be cleared.
13
PLL lock status. Indicates if the PLL is locked. The PLLLOCK bit is read-only. Writing to PLLLOCK has no effect.
PLLLOCK
0 PLL is not locked.
1 PLL is locked.
12
Limp mode enable. Selects between the PLL and the low-power clock divider as the source of all system clocks.
LIMP
0 Normal operation; PLL drives system clocks.
1 Limp mode; low-power clock divider drives system clocks.
Note: The transient behavior of the system when writing this bit cannot be predicted. When any USB wake-up
event is detected, this bit is cleared, LIMP mode is exited, and the PLL begins the process of relocking and
driving the system clocks.
11–9
Reserved, should be cleared.
8
LCDC internal clock enable. Selects whether the internal clock input to the LCD controller is enabled.
LCDCHEN
0 LCDC internal clock disabled
1 LCDC internal clock enabled
7
SSI RXD/TXD pull enable. Enables the internal weak pull cells on any external pin where the SSI receive data
SSIPUE
(RXD) function or SSI transmit data (TXD) function is available. The affected pins include SSI_RXD, SSI_TXD,
U1RXD, and U1TXD.
0 SSI data pin weak pull cells disabled.
1 SSI data pin weak pull cells enabled.
Note: The SSIPUE bit only enables the pull cells when the SSI RXD and TXD functions are currently selected
for the affected pins. See the
the SSI functions on those pins.
6
SSI RXD/TXD pull select. Selects whether the internal weak pull cells enabled by the SSIPUE bit are pull up or
SSIPUS
pull down.
0 SSI data pins are pulled down.
1 SSI data pins are pulled up.
Note: The SSIPUS bit has no effect when the SSIPUE bit is cleared.
Freescale Semiconductor
12
11
10
9
0
0
0
1
0
0
0
0
Figure 9-5. Miscellaneous Control Register (MISCCR)
Table 9-5. MISCCR Field Description
Chapter 13, "General Purpose I/O Module,"
MCF5329 Reference Manual, Rev 3
8
7
6
5
LCD
SSI
SSI
TIM
CHEN
PUE
PUS
DMA
0
1
1
1
Description
Chip Configuration Module (CCM)
Access: Supervisor read/write
4
3
2
1
0
0
SSI
USB
SRC
DIV
2
1
0
0
0
for information on how to enable
0
USB
SRC
1
9-5
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