Freescale Semiconductor MCF5329 Reference Manual page 616

Synchronous Serial Interface (SSI)
Field
31–10 Reserved, must be cleared.
9 Transmit bit 0 (Alignment). Allows SSI to transmit data word from bit position 0 or 15/31 in the transmit shift register.
TXBIT0 The shifting data direction can be msb or lsb first, controlled by the TSHFD bit.
0 msb-aligned. Shift with respect to bit 31 (if the word length is 16, 18, 20, 22 or 24) or bit 15 (if the word length is
8, 10 or 12) of the transmit shift register
1 lsb-aligned. Shift with respect to bit 0 of the transmit shift register
8 Transmit FIFO enable 1.
TFEN1 • When enabled, the FIFO allows eight samples to be transmitted by the SSI (per channel) (a ninth sample can be
shifting out) before SSI_ISR[TDE1] is set.
• When the FIFO is disabled, SSI_ISR[TDE1] is set when a single sample is transferred to the transmit shift register.
This issues an interrupt if the interrupt is enabled.
0 Transmit FIFO 1 disabled
1 Transmit FIFO 1 enabled
7 Transmit FIFO enable 0. Similar description as TFEN1, but pertains to Tx FIFO 0.
TFEN0 0 Transmit FIFO 0 disabled
1 Transmit FIFO 0 enabled
6 Frame sync direction. Controls the direction and source of the frame sync signal on the SSI_FS pin.
TFDIR 0 Frame sync is external
1 Frame sync generated internally
5 Clock direction. Controls the direction and source of the clock signal on the SSI_BCLK pin. Refer to
TXDIR details of clock port configuration.
0 Clock is external
1 Clock generated internally
4 Transmit shift direction. Controls whether the msb or lsb is transmitted first in a sample.
TSHFD 0 Data transmitted msb first
1 Data transmitted lsb first
3 Transmit clock polarity. Controls which bit clock edge is used to clock out data for the transmit section.
TSCKP 0 Data clocked out on rising edge of bit clock
1 Data clocked out on falling edge of bit clock
2 Transmit frame sync invert. Controls the active state of the frame sync I/O signal for the transmit section of SSI.
TFSI 0 Transmit frame sync is active high
1 Transmit frame sync is active low
1 Transmit frame sync length. Controls the length of the frame sync signal generated or recognized for the transmit
TFSL section. The length of a word-long frame sync is the same as the length of the data word selected by SSI_CCR[WL].
0 Transmit frame sync is one-word long
1 Transmit frame sync is one-bit-clock-period long
0 Transmit early frame sync. Controls when the frame sync is initiated for the transmit section. The frame sync signal
TEFS is deasserted after one bit for a bit length frame sync (TFSL = 1) and after one word for word length frame sync
(TFSL = 0). The frame sync can also be initiated upon receiving the first bit of data.
0 Transmit frame sync initiated as first bit of data transmits
1 Transmit frame sync is initiated one bit before the data transmits
24-22
Table 24-10. SSI_TCR Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Table 24-3 for
Freescale Semiconductor