Freescale Semiconductor MCF5329 Reference Manual page 129

Field
29 Enable store buffer.
ESB 0 All writes to write-through or noncachable imprecise space bypass the store buffer and generate bus cycles
directly. The associated performance penalty is described in
1 The four-entry FIFO store buffer is enabled; this buffer defers pending writes to write-through or cache-inhibited
imprecise regions to maximize performance.
Accesses to cache-inhibited, precise memory always bypass the store buffer.
28 Disable CPUSHL invalidation.
DPI 0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified and then invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified, then left valid.
27 Half cache lock mode
HLCK 0 Normal operation. The cache allocates the lowest non-valid way. If all ways are valid, the cache allocates the way
pointed at by the counter and then increments this counter modulo-4.
1 Half cache operation. The cache allocates to the lowest non-valid way of levels 2 and 3; if both ways are valid, the
cache allocates to way 2 if the high-order bit of the round-robin counter is zero; otherwise, it allocates way 3 and
then increments the round-robin counter modulo-2. This locks the content of ways 0 and 1. Ways 0 and 1 remain
updated on write hits and may be pushed and/or cleared by specific cache push/invalidate instructions.
This implementation allows maximum use of the available cache memory and also provides the flexibility of setting
HLCK before, during, or after the needed allocations occur.
26–25 Reserved, should be cleared.
24 Cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. After invalidation is complete, this bit
CINVA automatically returns to 0; it is not necessary to clear it explicitly. This bit is always read as a 0. Caches are not
cleared on power-up or normal reset, as shown in
0 No invalidation is performed
1 Initiate invalidation of the entire cache. The cache controller sequentially clears V and M bits in all sets.
Subsequent data accesses stall until the invalidation is finished, at which point, this bit is automatically cleared.
In copyback mode, the cache should be flushed using a CPUSHL instruction before setting this bit.
23–11 Reserved, should be cleared.
10 Default noncacheable fill buffer
DNFB 0 Fill buffer not used to store noncacheable instruction accesses (16 or 32 bits).
1 Fill buffer used to store noncacheable accesses. The fill buffer is used only for normal (TT = 0) instruction reads
of a noncacheable region. Instructions are loaded into the fill buffer by a burst access (same as a line fill). They
stay in the buffer until they are displaced, so subsequent accesses may not appear on the external bus.
Note: This feature can cause a coherency problem for self-modifying code. If enabled and a cache-inhibited access
uses the fill buffer, instructions remain valid in the fill buffer until a cache-invalidate-all instruction, another
cache-inhibited burst, or a miss that initiates a fill. A write to the line in the fill goes to the external bus without
updating or invalidating the buffer. Subsequent reads of that written data are serviced by the fill buffer and
receive stale information.
9–8 Default cache mode. Selects the default cache mode and access precision as follows:
DCM 00 Cacheable, write-through
01 Cacheable, copy-back
10 Cache-inhibited, precise exception model
11 Cache-inhibited, imprecise exception model. Precise and imprecise accesses are described in
"Cache-Inhibited
7–6 Reserved, should be cleared.
5 Default write protect. Indicates the default write privilege.
DW 0 Read and write accesses permitted
1 Write accesses not permitted
Freescale Semiconductor
Table 5-2. CACR Field Descriptions (continued)
Accesses."
MCF5329 Reference Manual, Rev 3
Description
Section 5.3.7.2.1, "Push and Store
Figure 5-5.
Cache
Buffers."
Section 5.3.4,
5-3