Fast Ethernet Controller (Fec); Introduction; Overview; Block Diagram - Freescale Semiconductor MCF5329 Reference Manual

Chapter 19

Fast Ethernet Controller (FEC)

19.1

Introduction

This chapter provides a feature-set overview, a functional block diagram, and transceiver connection
information for the 10 and 100 Mbps MII (media independent interface), as well as the 7-wire serial
interface. Additionally, detailed descriptions of operation and the programming model are included.
19.1.1

Overview

The Ethernet media access controller (MAC) supports 10 and 100 Mbps Ethernet/IEEE 802.3 networks.
An external transceiver interface and transceiver function are required to complete the interface to the
media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an
external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire
interface.
The module must be configured to enable the peripheral function of the
appropriate pins (refer to
to configuring the FEC.
19.1.2

Block Diagram

Figure 19-1 shows the block diagram of the FEC. The FEC is implemented with a combination of
hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3
standards.
Freescale Semiconductor
NOTE
Chapter 13, "General Purpose I/O
MCF5329 Reference Manual, Rev 3
Module") prior
19-1