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21.1.4.1
Low-Power Modes
The USB OTG module is integrated with the processor's low-power modes (stop, doze and wait). The
modes are implemented as follows:
•
Stop — The processor stops the clock to the USB OTG module. In this state, the USB OTG module
ignores traffic on the USB and does not generate any interrupts or wake-up events. The on-chip
transceiver is disabled to save power.
•
Wait — The clocks to the USB OTG module are running.
•
Doze — The processor stops the system clocks to the USB OTG module, but the 60 MHz
transceiver clock remains active. In doze mode, detection of resume signaling initiates a restart of
the module clocks.
21.2
External Signal Description
Table 21-2
describes the external signal functionality of the USB OTG module.
The ULPI signals are multiplexed with the FEC module. This section
describes the signal functions when in ULPI mode; refer to
"General Purpose I/O Module,"
Signal
I/O
USB_CLKIN
I
USBOTG_DM
I/O Data minus. Output of dual-speed transceiver for the USB OTG module.
USBOTG_DP
I/O Data plus. Output of dual-speed transceiver for the USB OTG module.
USBOTG_PU_EN O Enables an external pull-up on the USBOTG_DP line. This signal is controlled by the
Freescale Semiconductor
for more details.
Table 21-2. USB OTG Signal Descriptions
On-chip FS/LS transceiver
Optional 60 MHz clock source. This signal is also used for the input clock from a ULPI PHY.
State
Asserted—Data 1
Meaning
Negated—Data 0
Timing Asynchronous
State
Asserted—Data 1
Meaning
Negated—Data 0
Timing Asynchronous
UOCSR[BVLD] bit.
State
Asserted—Pull-up enabled. UOCSR[BVLD] set.
Meaning
Negated—Pull-up disabled. UOCSR[BVLD] cleared.
Timing Asynchronous
ULPI Interface
MCF5329 Reference Manual, Rev 3
Universal Serial Bus Interface – On-The-Go Module
NOTE
Description
Chapter 13,
21-5
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