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Field
7
Enable low-power mode entry. The mode entered is specified in LPCR[LPMD].
ENBWCR
0 Low-power mode entry is disabled
1 Low-power mode entry is enabled.
6–3
Reserved, should be cleared.
2–0
Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power
PRILVL
mode.
8.2.2
Peripheral Power Management Set Registers (PPMSR0 & PPMSR1)
The PPMSR registers provide a simple mechanism to set a given bit in the PPM{H,L}R registers to disable
the clock for a given peripheral module without the need to perform a read-modify write on the PPMR.
The data value on a register write causes the corresponding bit in the PPM{H,L}R to be set. The SAMCD
bit provides a global set function forcing the entire contents of the PPMR to be set, disabling all peripheral
module clocks. Reads of these registers return all zeroes.
Address: 0xFC04_002C (PPMSR0)
0xFC04_002E (PPMSR1)
7
R
0
W
Reset:
0
Figure 8-2. Peripheral Power Management Set Registers (PPMSRn)
Field
7
Reserved, should be cleared.
Freescale Semiconductor
Table 8-2. WCR Field Descriptions
PRILVL
Interrupt Level Needed to Exit Low-Power Mode
000
Any interrupt request exits low-power mode
001
Interrupt request levels [2-7] exit low-power mode
010
Interrupt request levels [3-7] exit low-power mode
011
Interrupt request levels [4-7] exit low-power mode
100
Interrupt request levels [5-7] exit low-power mode
101
Interrupt request levels [6-7] exit low-power mode
11x
Interrupt request level [7] exits low-power mode
6
5
0
0
SAMCD
0
0
Table 8-3. PPMSRn Field Descriptions
MCF5329 Reference Manual, Rev 3
Description
4
3
2
0
0
0
SMCD
0
0
0
Description
Power Management
Access: Supervisor Write-only
1
0
0
0
0
0
8-3
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