Memory Map/Register Definition - Freescale Semiconductor MCF5329 Reference Manual

2. The SDRAM controller must be placed in self-refresh mode to avoid data loss while the SDRAMC
is shut down.
7.1.3.4 Low-power Mode Operation
This subsection describes the operation of the clock module in low-power and halted modes of operation.
Low-power modes are described in
operation in low-power modes.
Low-power Mode
Wait
Doze
Stop
Halted
In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the core, and
SRAM are stopped. Each module can disable its clock locally at the module level.
In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL
or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time.
The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator
can also be disabled during stop mode, but requires a wakeup period to restart.
When the PLL is enabled in stop mode (LPCR[STPMD] = 00), the external FB_CLK signal can support
systems using FB_CLK as the clock source. See
for more information about operating the PLL in stop mode.
There is also a fast wakeup option for quickly enabling the system clocks during stop recovery
(LPCR[FWKUP]). This eliminates the wakeup recovery time but at the risk of sending a potentially
unstable clock to the system.
7.2

Memory Map/Register Definition

The PLL module programming model consists of the following registers:
Address
0xFC0C_0000 PLL Output Divider Register (PODR)
0xFC0C_0004 PLL Control Register (PCR)
Freescale Semiconductor
Chapter 8, "Power Management." Table 7-1
Table 7-1. Clock Module Operation in Low-power Modes
Clock Operation
Clocks sent to peripheral modules only
Clocks sent to peripheral modules only
All system clocks disabled
Normal
Section 8.2.5, "Low-Power Control Register (LPCR),"
Table 7-2. PLL Memory Map
Register
MCF5329 Reference Manual, Rev 3
shows the clock module
Mode Exit
Exit not caused by clock module, but normal
clocking resumes upon mode exit
Exit not caused by clock module, but normal
clocking resumes upon mode exit
Exit not caused by clock module, but clock
sources are re-enabled and normal clocking
resumes upon mode exit
Exit not caused by clock module
Width
Access Reset Value
(bits)
8 R/W 0x26
8 R/W 0x00
Clock Module
Section/Page
7.2.1/7-6
7.2.2/7-6
7-5