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Synchronous Serial Interface (SSI)
Field
3
Read command. Specifies whether the next frame carries an AC97 read command or not. When this bit is set, the
RD
corresponding tag bit (corresponding to command address slot of the next transmit frame) is automatically set. The
SSI automatically clears this bit after completing transmission of a frame.
0 Next frame does not have a read command
1 Next frame does have a read command
Note: Do not set WR and RD at the same time.
2
Tag in FIFO. Controls the destination of the information received in the AC97 tag slot (slot #0).
TIF
0 Tag information stored in SSI_ATAG register
1 Tag information stored in Rx FIFO 0
1
Fixed/variable operation.
FV
0 AC97 fixed mode
1 AC97 variable mode
0
AC97 mode enable. Refer to
AC97EN
0 AC97 mode disabled
1 AC97 mode enabled
24.3.15 SSI AC97 Command Address Register (SSI_ACADD)
SSI_ACADD contains the command address slot information.
Address: 0xFC0B_C03C (SSI_ACADD)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 24-22. SSI AC97 Command Address Register (SSI_ACADD)
Field
31–19
Reserved, must be cleared.
18–0
AC97 command address. Stores the command address slot information (bit 19 of the slot is sent in accordance with
ACADD
the SSI_ACR[WR and RD] bits). A direct write from the core or the information received in the incoming command
address slot can update these bits. If contents of these bits change due to an update, the SSI_ISR[CMDAU] bit is set.
24-28
Table 24-15. SSI_ACR Field Descriptions (continued)
Section 24.4.1.5, "AC97 Mode,"
Table 24-16. SSI_ACADD Field Descriptions
MCF5329 Reference Manual, Rev 3
Description
for details of AC97 operation.
ACADD
Description
Access: User read/write
8
7
6
5
4
3
2
1
0
Freescale Semiconductor
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