Table of Contents
Advertisement
•
Chapter 30, "Queued Serial Peripheral Interface (QSPI),"
and a description of operation, including details of the QSPI's internal storage organization.
The chapter concludes with the programming model and a timing diagram.
•
Chapter 31, "UART Modules,"
receiver/transmitters (UARTs) implemented on the device and includes programming
examples.
•
Chapter 32, "I2C Interface,"
synchronization, and I
•
Chapter 33, "Message Digest Hardware Accelerator (MDHA),"
of two of the world's most popular cryptographic hash functions: SHA-1 and MD5.
Accelerators for either algorithm separately have been designed, however the MDHA
combines similar functions of the two algorithms into one small, optimized area of silicon
on the device.
•
Chapter 34, "Random Number Generator (RNG),"
Generator (RNG), including a programming model, functional description, and application
information.
•
Chapter 35, "Symmetric Key Hardware Accelerator (SKHA),"
hardware coprocessor designed to implement two widely used symmetric key block cipher
algorithms, AES and DES.
•
Chapter 36, "Debug Module,"
•
Chapter 37, "IEEE 1149.1 Test Access Port (JTAG),"
operation of the Joint Test Action Group (JTAG) implementation. It describes those items
required by the IEEE 1149.1 standard and provides additional information specific to the
device. For internal details and sample applications, see the IEEE 1149.1 document.
This manual includes the following appendices:
•
Appendix A, "Register Memory Map Quick Reference,"
for memory-mapped registers.
•
Appendix B, "Revision History,"
versions of this document.
Suggested Reading
This section lists additional reading that provides background for the information in this manual
as well as general information about the ColdFire architecture.
Hardware Specification
The MCF5329EC document contains the mechanical and electrical specifications of the
MCF52329. It can be found at http://www.freescale.com/coldfire.
xxxii
describes the use of the universal asynchronous
2
describes the I
C module, including I
2
C programming model registers.
describes the hardware debug support in the device.
provides a revision history for all previously released
MCF5329 Reference Manual, Rev 3
provides a feature-set overview
2
C protocol, clock
describes implementation
describes the 32-bit Random Number
describes the cryptographic
describes configuration and
provides the entire address map
Freescale Semiconductor
Advertisement
Table of Contents
