Table of Contents
Advertisement
Message Digest Hardware Accelerator (MDHA)
MDMR bit settings
SSL=1
SWAP=1
33.2.2
MDHA Control Register (MDCR)
The MDCR contains bits that should be set following a hardware reset.
Address: 0xEC08_0004 (MDCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–21
Reserved, should be cleared.
20–16
DMA request level. Represents the minimum number of words available in the FIFO between DMA requests. For
DMAL
example: When DMAL is programmed to 5 longwords, the DMA request signal is not asserted until there is space in
the input FIFO for 5 longwords. This value must be 16 longwords or less.
00001–10000 = 1–16 words
All others reserved.
15–3
Reserved, should be cleared.
2
Endian select
END
0 Little endian mode
1 Big endian mode
1
DMA enable. Enables/disables DMA requests from the MDHA module.
DMA
0 Disable DMA requests
1 Enable DMA requests
0
Interrupt enable. Enables/disables interrupts from the MDHA module.
IE
0 Disable interrupts
1 Enable interrupts
33-6
Table 33-3. Invalid MDMR Bit Settings
ALG=0
SSL MAC is only functional for the MD5 algorithm.
(SHA-1)
ALG=1
The SWAP bit is designed to support a particular function for the
(MD5)
SHA-1 algorithm and is invalid for MD5.
DMAL
Figure 33-3. MDHA Control Register (MDCR)
Table 33-4. MDCR Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Comments
8
7
0 0 0 0 0 0 0 0 0 0 0 0 0
Access: User read/write
6
5
4
3
2
1
0
END DMA
IE
0
0
0
Freescale Semiconductor
Advertisement
Table of Contents
