Freescale Semiconductor MCF5329 Reference Manual page 11

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11.2.2 Master Privilege Register 1 (MPR1) ............................................................................. 11-4
11.2.3 Peripheral Access Control Registers (PACR
11.2.4 Bus Monitor Timeout Registers (BMT
11.2.5 Core Watchdog Control Register (CWCR) ................................................................... 11-8
11.2.6 Core Watchdog Service Register (CWSR) .................................................................... 11-9
11.2.7 SCM Interrupt Status Register (SCMISR)................................................................... 11-10
11.2.8 Burst Configuration Register (BCR) ........................................................................... 11-10
11.2.9 Core Fault Address Register (CFADR) ....................................................................... 11-11
11.2.10 Core Fault Interrupt Enable Register (CFIER) ............................................................ 11-12
11.2.11 Core Fault Location Register (CFLOC) ...................................................................... 11-12
11.2.12 Core Fault Attributes Register (CFATR)..................................................................... 11-12
11.2.13 Core Fault Data Register (CFDTR) ............................................................................. 11-13
11.3 Functional Description ............................................................................................................... 11-14
11.3.1 Access Control ............................................................................................................. 11-14
11.3.2 Core Watchdog Timer ................................................................................................. 11-14
11.3.3 Core Data Fault Recovery Registers............................................................................ 11-15
12.1 Overview ...................................................................................................................................... 12-1
12.2 Features ........................................................................................................................................ 12-3
12.3 Modes of Operation...................................................................................................................... 12-3
12.4 Memory Map / Register Definition.............................................................................................. 12-3
12.4.1 XBS Priority Registers (XBS_PRS
12.4.2 XBS Control Registers (XBS_CRS
12.5 Functional Description ................................................................................................................. 12-6
12.5.1 Arbitration...................................................................................................................... 12-6
12.6 Initialization/Application Information ......................................................................................... 12-7
13.1 Introduction .................................................................................................................................. 13-1
13.1.1 Overview........................................................................................................................ 13-2
13.1.2 Features .......................................................................................................................... 13-3
13.2 External Signal Description ......................................................................................................... 13-3
13.3 Memory Map/Register Definition.............................................................................................. 13-11
13.3.1 Port Output Data Registers (PODR_
13.3.2 Port Data Direction Registers (PDDR_
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Contents
Title
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Chapter 12
Crossbar Switch (XBS)
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Chapter 13
General Purpose I/O Module
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) ........................................................................ 13-14
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) .................................................................... 13-17
MCF5329 Reference Manual, Rev 3
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