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General Purpose I/O Module
FEC_TXCLK / PFECH7
FEC_TXEN / PFECH6
FEC_TXD0 / ULPI_DATA0 / PFECH5
Port
FEC_COL / ULPI_CLK / PFECH4
FECH
FEC_RXCLK / ULPI_NXT / PFECH3
FEC_RXDV / ULPI_STP / PFECH2
FEC_RXD0 / ULPI_DATA4 / PFECH1
FEC_CRS / ULPI_DIR / PFECH0
FEC_TXD[3:1] / ULPI_DATA[3:1] / PFECL[7:5]
Port
FEC_TXER / PFECL4
FECL
FEC_RXD[3:1] / ULPI_DATA[7:5] / PFECL[3:1]
FEC_RXER / PFECL0
OE / PBUSCTL3
TA / PBUSCTL2
Port
BUSCTL
R/W / PBUSCTL1
TS / DACK0 / PBUSCTL0
Port
BE/BWE[3:0] / PBE[3:0]
BE
Port
FB_CS[5:2] / PCS[5:2]
CS
FB_CS1 / SD_CS1 / PCS1
PWM[7,5] / PPWM[7,5]
Port
PWM3 / DT3IN / DT3OUT / PPWM3
PWM
PWM1 / DT2IN / DT2OUT / PPWM1
IRQ7 / PIRQ7
IRQ6 / USBH_VBUS_EN / PIRQ6
IRQ5 / USBH_VBUS_OC / PIRQ5
IRQ4 / SSI_MCLK / PIRQ4
Port
IRQ3 / PIRQ3
IRQ
IRQ2 / USB_CLKIN / PIRQ2
IRQ1 / SSI_CLKIN / DREQ1 / PIRQ1
SSI_MCLK / PSSI4
SSI_BCLK / PWM7 / U2CTS / PSSI3
Port
SSI_FS / PWM5 / U2RTS / PSSI2
SSI
SSI_RXD / CANRX / U2RXD / PSSI1
SSI_TXD / CANTX / U2TXD / PSSI0
Pin Assignment Control
13.1.1
Overview
The GPIO module controls the configuration for various external pins, including those used for:
•
External bus accesses
•
External chip selection
•
Ethernet data and control
2
•
I
C serial control
•
QSPI
•
32-bit DMA timers
13-2
Drive Strength Control
Figure 13-1. Ports Module Block Diagram
MCF5329 Reference Manual, Rev 3
FEC_MDC / I2C_SCL / PFECI2C3
FEC_MDIO / I2C_SDA / PFECI2C2
Port
I2C_SCL / U2TXD / CANTX / PFECI2C1
FECI2C
I2C_SDA / U2RXD / CANRX / PFECI2C0
U1CTS / SSI_BCLK / PUART7
U1RTS / SSI_FS / PUART6
U1TXD / SSI_TXD / PUART5
Port
U1RXD / / SSI_RXD / PUART4
UART
U0CTS / PUART3
U0RTS / PUART2
U0TXD / PUART1
U0RXD / PUART0
QSPI_CS2 / U2RTS / PQSPI5
QSPI_CS1 / USBOTG_PU_EN / PWM7 / PQSPI4
Port
QSPI_CS0 / PWM5 / PQSPI3
QSPI
QSPI_CLK / I2C_SCL / PQSPI2
QSPI_DIN / U2CTS / PQSPI1
QSPI_DOUT / I2C_SDA / PQSPI0
DT3IN / DT3OUT / U2RXD / PTIMER3
Port
DT2IN / DT2OUT / U2TXD / PTIMER2
TIMER
DT1IN / DT1OUT / DACK1 / PTIMER1
DT0IN / DT0OUT / DREQ0 / PTIMER0
Port
LCD_D17 / CANTX / PLCDDATAH1
LCD_D16 / CANRX / PLCDDATAH0
LCDDATAH
Port
LCD_D[15:8] / PLCDDATAM[7:0]
LCDDATAM
Port
LCD_D[7:0] / PLCDDATAL[7:0]
LCDDATAL
OE/ACD / PLCDCTL8
CLS / PLCDCTL7
CONTRAST / PLCDCTL6
FLM/VSYNC / PLCDCTL5
Port
LP/HSYNC / PLCDCTL4
LCDCTLL
LSCLK / PLCDCTL3
PS / PLCDCTL2
REV / PLCDCTL1
SPL_SPR / PLCDCTL0
Internal Bus
Freescale Semiconductor
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