Freescale Semiconductor MCF5329 Reference Manual page 558

Liquid Crystal Display Controller (LCDC)
Operation of the panel interface is accomplished in the following steps:
1. LCD_LSCLK clocks the pixel data into the display driver's internal shift register.
2. LCD_LP signifies the end of the current line of serial data and latches the shifted pixel data into a
wide latch.
3. LCD_FLM marks the first line of the displayed page. The LCD_D (and the associated LCD_LP),
enclosed by the LCD_FLM signal, marks the first line of the current frame.
4. LCD_ACD toggles after a pre-programmed number of LCD_FLM pulses. This signal refreshes the
LCD panel.
The LCD_D bus width is programmable to 1, 2, 4, or 8 bits in monochrome
mode (the COLOR bit in the panel configuration register is set to 0). Data is
justified to the least significant bits of the LCD_D[17:0] bus. Passive color
displays use a fixed 2-2/3 pixels of data per 8-bit vector as shown in
Figure 22-37.
LCD_FLM
LCD_LP
LCD_LP
LCD_LSCLK
LCD_D0
LCD_D1
LCD_D2
LCD_D3
Figure 22-36. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels
22-38
NOTE
LINE 1 LINE 2 LINE 3 LINE 4
1 2 3
[0,0] [0,4] [0,8]
[0,1] [0,5] [0,9]
[0,2] [0,6] [0,10]
[0,7] [0,11]
[0,3]
MCF5329 Reference Manual, Rev 3
LINE n LINE 1
59 60 m/4-1
[0,232] [0,236] [0,m-8] [0,m-4]
[0,233] [0,237] [0,m-7] [0,m-3]
[0,234] [0,238] [0,m-6] [0,m-2]
[0,235] [0,239] [0,m-5] [0,m-1]
m/4
Freescale Semiconductor