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SDRAM Controller (SDRAMC)
For 32-bit data bus configuration:
If all devices' row address width is 12 bits, the column address can be ≥ 8 bits.
•
If all devices' row address width is 13 bits, the column address can be ≥ 8 bits.
•
If all devices' column address width is 8 bits, the row address can be ≥ 11 bits.
•
•
The maximum row bits plus column bits equals 24.
•
x8 and x16 data width memory devices can be mixed (but not in the same space).
•
x32 data width memory devices cannot be mixed with any other width.
For 16-bit data bus configuration:
If all devices' row address width is 12 bits, the column address can be ≥ 9 bits.
•
If all devices' row address width is 13 bits, the column address can be ≥ 9 bits.
•
If all devices' column address width is 9 bits, the row address can be ≥ 11 bits.
•
•
The maximum row bits plus column bits equals 25.
•
x16 data width memory devices cannot be mixed with any other width.
18.3.2
SDRAM SDR Connections
Figure 18-2
shows a block diagram using 32-bit wide SDR SDRAM (such as Micron MT48LC4M32B2)
and flash (such as Spansion AM29LV160D). SDR design requires special timing consideration for the
SD_DQS[3: ] signals. For reads from DDR SDRAMs, the memory drives the DQS pins so that the data
2
lines and DQS signals have concurrent edges. The SDRAMC is designed to latch data 1/4 clock after the
SD_DQS[3: ] edge. For DDR SDRAM, this ensures that the latch time is in the middle of the data valid
2
window.
The SDRAMC also uses the SD_DQS[3: ] signals to determine when read data can be latched for SDR
SDRAM; however, SDR memories do not provide DQS outputs. Instead the SDRAMC provides a
SD_SDRDQS output routed back into the controller as SD_DQS[3: ]. The SD_SDRDQS signal should
be routed such that the valid data from the SDRAM reaches the controller at the same time or before the
SD_SDRDQS reaches the SD_DQS[3: ] inputs.
When routing SD_SDRDQS the outbound trace length should be matched to the SD_CLK trace length.
This aligns SD_SDRDQS to the SD_CLK as if the memory had generated the DQS pulse. The inbound
trace should be routed along the data path, which should synchronize the SD_DQS so that the data is
latched in the middle of the data valid window.
18-10
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2
MCF5329 Reference Manual, Rev 3
2
Freescale Semiconductor
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