Memory Map/Register Definition - Freescale Semiconductor MCF5329 Reference Manual

System Control Module (SCM)
• Core fault reporting registers
11.2

Memory Map/Register Definition

The memory map for the SCM registers is shown in
Attempted accesses to reserved addresses result in a bus error, while attempted writes to read-only registers
are ignored and do not terminate with an error. Unless noted otherwise, writes to the programming model
must match the size of the register, e.g., an 8-bit register only supports 8-bit writes, etc. Attempted writes
of a different size than the register width produce a bus error and no change to the targeted register.
Address
1
0xEC00_0000 Master Privilege Register 1 (MPR1)
1
0xEC00_0054 Bus Monitor Timeout 1 (BMT1)
0xFC00_0000 Master Privilege Register 0 (MPR0)
0xFC00_0020 Peripheral Access Control Register A (PACRA)
0xFC00_0024 Peripheral Access Control Register B (PACRB)
0xFC00_0028 Peripheral Access Control Register C (PACRC)
0xFC00_002C Peripheral Access Control Register D (PACRD)
0xFC00_0040 Peripheral Access Control Register E (PACRE)
0xFC00_0044 Peripheral Access Control Register F (PACRF)
0xFC00_0048 Peripheral Access Control Register G (PACRG)
1
0xEC00_0040 Peripheral Access Control Register H (PACRH)
0xFC00_0054 Bus Monitor Timeout 0 (BMT0)
0xFC04_0013 Wakeup Control Register (WCR)
0xFC04_0016 Core Watchdog Control Register (CWCR)
0xFC04_001B Core Watchdog Service Register (CWSR)
0xFC04_001F SCM Interrupt Status Register (SCMISR)
0xFC04_0024 Burst Configuration Register (BCR)
0xFC04_0070 Core Fault Address Register (CFADR)
0xFC04_0075 Core Fault Interrupt Enable Register (CFIER)
0xFC04_0076 Core Fault Location Register (CFLOC)
0xFC04_0077 Core Fault Attributes Register (CFATR)
0xFC04_007C Core Fault Data Register (CFDTR)
1
Take note of register location.
2
The WCR register is described in
11-2
Table
Table 11-1. SCM Memory Map
Register
2
Chapter 8, "Power Management."
MCF5329 Reference Manual, Rev 3
11-1.
Width
Access Reset Value
(bits)
32 R/W 0x7000_0007
32 R/W 0x0000_0008
32 R/W 0x7777_7777
32 R/W 0x5444_4444
32 R/W 0x4444_4444
32 R/W 0x4444_4444
32 R/W 0x4444_4444
32 R/W 0x4444_4444
32 R/W 0x4444_4444
32 R/W 0x4444_4444
32 R/W 0x4444_4444
32 R/W 0x0000_0008
8 R/W
16 R/W 0x0000
8 R/W Undefined
8 R/W
32 R/W 0x0000_0000
32 R 0x0000_0000
8 R/W
8 R Undefined
8 R Undefined
32 R Undefined
Section/Page
11.2.1/11-3
11.2.4/11-7
11.2.1/11-3
11.2.3/11-4
11.2.3/11-4
11.2.3/11-4
11.2.3/11-4
11.2.3/11-4
11.2.3/11-4
11.2.3/11-4
11.2.3/11-4
11.2.4/11-7
0x00 8.2.1/8-2
11.2.5/11-8
11.2.6/11-9
0x00 11.2.7/11-10
11.2.8/11-10
11.2.9/11-11
0x00 11.2.10/11-12
11.2.11/11-12
11.2.12/11-12
11.2.13/11-13
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