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Chapter 17
FlexBus
17.1
Introduction
This chapter describes external bus data transfer operations and error conditions. It describes transfers
initiated by the ColdFire processor (or any other bus master) and includes detailed timing diagrams
showing the interaction of signals in supported bus operations.
In this chapter, unless otherwise noted, clock refers to the FB_CLK used for
the external bus (f
The external data bus is shared between the FlexBus module and the
SDRAM controller. When the SDRAM controller is in SDR mode
(DRAMSEL = 1), the data bus is switched dynamically between the
SDRAM controller and the FlexBus module. However, when the SDRAM
controller is in DDR mode (DRAMSEL = 0), D[31:16] is dedicated to the
SDRAM data bus and D[15:0] is dedicated to the FlexBus data bus. In this
case, external pins D[15:0], are mapped internally to the upper two bytes of
the FlexBus data bus, FB_D[31:16]. This chapter only uses FB_D[31:0] or
FB_D[31:X] to designate the data bus, but the actual pins used depend on
the DRAMSEL setting. Take this into consideration throughout this chapter.
17.1.1
Overview
A multi-function external bus interface called the FlexBus interface controller is provided on the device
with basic functionality of interfacing to slave-only devices with a maximum bus frequency up to 80 MHz.
It can be directly connected to the following asynchronous or synchronous devices with little or no
additional circuitry:
•
External boot ROMs
•
Flash memories
•
Gate-array logic
•
Other simple target (slave) devices
For asynchronous devices, a simple chip-select based interface can be used.
The FlexBus interface has up to six general purpose chip-selects, FB_CS[5:0]. The actual number of chip
selects available depends upon the device and its pin configuration. See
Chip-select FB_CS0 can be dedicated to boot memory access and programmed to be byte (8 bits), word
Freescale Semiconductor
NOTE
).
sys/3
MCF5329 Reference Manual, Rev 3
Table 13-1
for more details.
17-1
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