Pll Frequency Multiplication Factor Select - Freescale Semiconductor MCF5329 Reference Manual

Clock Module
Frequency
of a PLL
output clock
After reset, the PCR and PMDR registers are cleared, disabling dithering. After reset has been de-asserted
and the PLL has locked (indicated by the MISCCR[PLLLOCK] bit), the dithering waveform definition
may be changed by writing to the PCR[DITHDEV] field and the PMDR register. However, the
PCR[DITHDEV] field and PMDR register may only be written to when the PLL is in non-dithered
operation (i.e. the PCR[DITHEN] bit must be cleared).
Writing to the PCR[DITHDEV] field or the PMDR during dithering
operation results in unpredictable PLL operation.
The dither deviation can be programmed to be between -0.75% of the non-dithered frequency up to -2.50%
of the non-dithered frequency in steps of 0.25%.
The dither deviation settings in the PCR[DITHDEV] field are target
percentages based on simulation. The actual percentages achieved may be
numerically different than the percentages listed in the specification;
however, the actual percentages achieved are in proportion to each other and
are stable within ±10% across process, voltage, and temperature conditions.
The dither modulation frequency can be programmed to be between approximately 10kHz and 100kHz.
Because the dither modulation frequency is determined as a division of the input frequency, the dither
modulation frequency is given by the following equation:
Dither Modulation Frequency
PMDR[MODDIV] field values that result in a dither modulation frequency
greater than 105kHz or less than 9.95kHz are invalid and result in
unpredictable PLL operation.
7.3.3

PLL Frequency Multiplication Factor Select

The frequency multiplication factor of the PLL is defined by the feedback divider in the following
equation:
7-10
Modulation period
Figure 7-7. Ideal Triangular Dithering Waveform
NOTE
NOTE
------------------------------------------------------------- -
=
PMDR MODDIV
NOTE
⎛
PFDR
×
-------------------------------------------------- -
f = f
⎝
×
sys ref
4 PODR[CPUDIV]
MCF5329 Reference Manual, Rev 3
Percent Frequency
Input Frequency
[ ] ×
32
⎞
⎠
Deviation
Time
Eqn. 7-1
Eqn. 7-2
Freescale Semiconductor